From 5034af30382d2e22a7898ae6e2f500646ac11573 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Thu, 8 Dec 2011 21:25:05 +0100
Subject: [PATCH] Corelogic conversion example

---
 examples/corelogic_conv.py |  9 +++++++
 examples/divider_conv.py   | 50 --------------------------------------
 migen/corelogic/divider.py |  3 ++-
 3 files changed, 11 insertions(+), 51 deletions(-)
 create mode 100644 examples/corelogic_conv.py
 delete mode 100644 examples/divider_conv.py

diff --git a/examples/corelogic_conv.py b/examples/corelogic_conv.py
new file mode 100644
index 000000000..cd141ccee
--- /dev/null
+++ b/examples/corelogic_conv.py
@@ -0,0 +1,9 @@
+from migen.fhdl import structure as f
+from migen.fhdl import verilog
+from migen.corelogic import roundrobin, divider
+
+r = roundrobin.Inst(5)
+d = divider.Inst(16)
+frag = r.GetFragment() + d.GetFragment()
+o = verilog.Convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
+print(o)
\ No newline at end of file
diff --git a/examples/divider_conv.py b/examples/divider_conv.py
deleted file mode 100644
index 6696fdb86..000000000
--- a/examples/divider_conv.py
+++ /dev/null
@@ -1,50 +0,0 @@
-from migen.fhdl import structure as f
-from migen.fhdl import verilog
-from functools import partial
-
-class Divider:
-	def __init__(self, w):
-		self.w = w
-		
-		d = partial(f.Declare, self)
-		
-		d("start_i")
-		d("dividend_i", f.BV(w))
-		d("divisor_i", f.BV(w))
-		d("ready_o")
-		d("quotient_o", f.BV(w))
-		d("remainder_o", f.BV(w))
-		
-		d("_qr", f.BV(2*w))
-		d("_counter", f.BV(f.BitsFor(w)))
-		d("_divisor_r", f.BV(w))
-		d("_diff", f.BV(w+1))
-	
-	def GetFragment(self):
-		a = f.Assign
-		comb = [
-			a(self.quotient_o, self._qr[:self.w]),
-			a(self.remainder_o, self._qr[self.w:]),
-			a(self.ready_o, self._counter == f.Constant(0, self._counter.bv)),
-			a(self._diff, self.remainder_o - self._divisor_r)
-		]
-		sync = [
-			f.If(self.start_i == 1, [
-				a(self._counter, self.w),
-				a(self._qr, self.dividend_i),
-				a(self._divisor_r, self.divisor_i)
-			], [
-				f.If(self.ready_o == 0, [
-					f.If(self._diff[self.w] == 1,
-						[a(self._qr, f.Cat(0, self._qr[:2*self.w-1]))],
-						[a(self._qr, f.Cat(1, self._qr[:self.w-1], self._diff[:self.w]))]),
-					a(self._counter, self._counter - f.Constant(1, self._counter.bv)),
-				])
-			])
-		]
-		return f.Fragment(comb, sync)
-
-d = Divider(32)
-frag = d.GetFragment()
-o = verilog.Convert(frag, {d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
-print(o)
\ No newline at end of file
diff --git a/migen/corelogic/divider.py b/migen/corelogic/divider.py
index e19ffc2bf..4fffda08d 100644
--- a/migen/corelogic/divider.py
+++ b/migen/corelogic/divider.py
@@ -1,4 +1,5 @@
 from migen.fhdl import structure as f
+from functools import partial
 
 class Inst:
 	def __init__(self, w):
@@ -40,4 +41,4 @@ class Inst:
 				])
 			])
 		]
-		return f.Fragment(comb, sync)
\ No newline at end of file
+		return f.Fragment(comb, sync)