From 505c8b85d6be58b291021c8a16b0e19535715a36 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 29 Jul 2021 17:16:38 +0200 Subject: [PATCH] soc/add_spi_flash: Reduce LiteSPIPHY default divisor to max(2, self.sys_clk_freq/clk_freq). One small FPGAs running the BIOS from SPI Flash, the default divisor of 9 was slowing down too much BIOS boot time (It was OK on reboot after liblitespi auto-calibration). Reduce the default divisor to avoid this. --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 9d03ce75d..a8ca903f8 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1514,7 +1514,7 @@ class LiteXSoC(SoC): self.check_if_exists(name + "_phy") self.check_if_exists(name + "_mmap") spiflash_pads = self.platform.request(name if mode == "1x" else name + mode) - spiflash_phy = LiteSPIPHY(spiflash_pads, module) + spiflash_phy = LiteSPIPHY(spiflash_pads, module, default_divisor=max(int(self.sys_clk_freq/clk_freq), 2)) spiflash_mmap = LiteSPI(spiflash_phy, clk_freq=clk_freq, mmap_endianness=self.cpu.endianness, **kwargs) setattr(self.submodules, name + "_phy", spiflash_phy) setattr(self.submodules, name + "_mmap", spiflash_mmap)