From 5061a368daa9028c7720f10aec25286e09687099 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 9 Jun 2021 08:25:23 +0200
Subject: [PATCH] cores/video: Regroup VGA/DVI Phy in VideoGenericPHY and
 support variations (positive/negative hsync/vsync, etc...)

---
 litex/soc/cores/video.py | 64 ++++++++++++++++------------------------
 1 file changed, 25 insertions(+), 39 deletions(-)

diff --git a/litex/soc/cores/video.py b/litex/soc/cores/video.py
index 202bff480..62f45d143 100644
--- a/litex/soc/cores/video.py
+++ b/litex/soc/cores/video.py
@@ -656,36 +656,9 @@ class VideoFrameBuffer(Module, AutoCSR):
 
 class Open(Signal): pass
 
-# VGA (Generic).
+# Generic (Very Generic PHY supporting VGA/DVI and variations).
 
-class VideoVGAPHY(Module):
-    def __init__(self, pads, clock_domain="sys"):
-        self.sink = sink = stream.Endpoint(video_data_layout)
-
-        # # #
-
-        # Always ack Sink, no backpressure.
-        self.comb += sink.ready.eq(1)
-
-        # Drive VGA Clk (Optional).
-        if hasattr(pads, "clk"):
-            self.comb += pads.clk.eq(ClockSignal(clock_domain))
-
-        # Drive VGA Conrols.
-        self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain))
-        self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain))
-
-        # Drive VGA Datas.
-        cbits  = len(pads.r)
-        cshift = (8 - cbits)
-        for i in range(cbits):
-            self.specials += SDROutput(i=sink.r[cshift + i], o=pads.r[i], clk=ClockSignal(clock_domain))
-            self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
-            self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
-
-# DVI (Generic).
-
-class VideoDVIPHY(Module):
+class VideoGenericPHY(Module):
     def __init__(self, pads, clock_domain="sys", with_clk_ddr_output=True):
         self.sink = sink = stream.Endpoint(video_data_layout)
 
@@ -694,19 +667,24 @@ class VideoDVIPHY(Module):
         # Always ack Sink, no backpressure.
         self.comb += sink.ready.eq(1)
 
-        # Drive DVI Clk.
-        if with_clk_ddr_output:
-            self.specials += DDROutput(i1=1, i2=0, o=pads.clk, clk=ClockSignal(clock_domain))
-        else:
-            self.comb += pads.clk.eq(ClockSignal(clock_domain))
+        # Drive Clk.
+        if hasattr(pads, "clk"):
+            if with_clk_ddr_output:
+                self.specials += DDROutput(i1=1, i2=0, o=pads.clk, clk=ClockSignal(clock_domain))
+            else:
+                self.comb += pads.clk.eq(ClockSignal(clock_domain))
 
-        # Drive DVI Controls.
+        # Drive Controls.
         if hasattr(pads, "de"):
-            self.specials += SDROutput(i=sink.de,    o=pads.de,    clk=ClockSignal(clock_domain))
-        self.specials += SDROutput(i=sink.hsync, o=pads.hsync, clk=ClockSignal(clock_domain))
-        self.specials += SDROutput(i=sink.vsync, o=pads.vsync, clk=ClockSignal(clock_domain))
+            self.specials += SDROutput(i=sink.de, o=pads.de, clk=ClockSignal(clock_domain))
+        if hasattr(pads, "hsync_n") and hasattr(pads, "vsync_n"):
+            self.specials += SDROutput(i=~sink.hsync, o=pads.hsync_n, clk=ClockSignal(clock_domain))
+            self.specials += SDROutput(i=~sink.vsync, o=pads.vsync_n, clk=ClockSignal(clock_domain))
+        else:
+            self.specials += SDROutput(i=sink.hsync,  o=pads.hsync,   clk=ClockSignal(clock_domain))
+            self.specials += SDROutput(i=sink.vsync,  o=pads.vsync,   clk=ClockSignal(clock_domain))
 
-        # Drive DVI Datas.
+        # Drive Datas.
         cbits  = len(pads.r)
         cshift = (8 - cbits)
         for i in range(cbits):
@@ -714,6 +692,14 @@ class VideoDVIPHY(Module):
             self.specials += SDROutput(i=sink.g[cshift + i], o=pads.g[i], clk=ClockSignal(clock_domain))
             self.specials += SDROutput(i=sink.b[cshift + i], o=pads.b[i], clk=ClockSignal(clock_domain))
 
+# VGA (Generic).
+
+class VideoVGAPHY(VideoGenericPHY): pass
+
+# DVI (Generic).
+
+class VideoDVIPHY(VideoGenericPHY): pass
+
 # HDMI (Generic).
 
 class VideoHDMI10to1Serializer(Module):