From 5079a3c32e45d026eefa22d922b2dc58b9edacd8 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Sun, 12 Jan 2020 19:52:42 +1000 Subject: [PATCH] uart: add BridgedUart This version of the UART adds a second, compatible UART after the first. This maintians software compatibility, and allows a program running on the other side of the litex bridge to act as a terminal emulator by manually reading and writing the second UART. Signed-off-by: Sean Cross --- litex/soc/cores/uart.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index 2bdc8e30e..0a21838cf 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -267,3 +267,26 @@ class UARTMultiplexer(Module): uarts[n].rx.eq(uart.rx) ] self.comb += Case(self.sel, cases) + +class BridgedUart(UART): + """ + Creates a UART that's fully compatible with the existing + UART class, except it adds a second UART that can be read + over the Wishbone bridge. + + This allows a program on the other end of the Wishbone + bridge to act as a terminal emulator on a board where + the UART is otherwise used as a Wishbone bridge. + """ + def __init__(self, **kw): + class BridgedUartPhy: + def __init__(self): + self.sink = stream.Endpoint([("data", 8)]) + self.source = stream.Endpoint([("data", 8)]) + class CrossoverPhy: + def __init__(self, phy): + self.source = phy.sink + self.sink = phy.source + phy = BridgedUartPhy() + UART.__init__(self, phy, **kw) + self.submodules.xover = UART(CrossoverPhy(phy))