From 50e5df4ffbb8380e4d9e72791ec2ab18c0bc5766 Mon Sep 17 00:00:00 2001
From: Piotr Wegrzyn <piotro@piotro.eu>
Date: Fri, 13 Dec 2024 22:33:39 +0100
Subject: [PATCH] soc/ethernet: enable full_memory_we by default for Quartus
 toolchain

---
 litex/soc/integration/soc.py | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index e523a33d2..e2c75861d 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1841,7 +1841,7 @@ class LiteXSoC(SoC):
         data_width              = 8,
         nrxslots                = 2, rxslots_read_only  = True,
         ntxslots                = 2, txslots_write_only = False,
-        full_memory_we          = False,
+        full_memory_we          = None,
         with_timestamp          = False,
         with_timing_constraints = True,
         local_ip                = None,
@@ -1850,6 +1850,7 @@ class LiteXSoC(SoC):
         # Imports
         from liteeth.mac import LiteEthMAC
         from liteeth.phy.model import LiteEthPHYModel
+        from litex.build.altera.quartus import AlteraQuartusToolchain
 
         # MAC.
         assert data_width in [8, 32, 64]
@@ -1857,6 +1858,8 @@ class LiteXSoC(SoC):
         self.check_if_exists(name)
         if with_timestamp:
             self.timer0.add_uptime()
+        if full_memory_we is None:
+            full_memory_we = isinstance(self.platform.toolchain, AlteraQuartusToolchain)
         ethmac = LiteEthMAC(
             phy               = phy,
             dw                = {8: 32, 32: 32, 64: 64}[data_width],