diff --git a/litex/compat/soc_sdram.py b/litex/compat/soc_sdram.py
index 1f9373150..16ac21dad 100644
--- a/litex/compat/soc_sdram.py
+++ b/litex/compat/soc_sdram.py
@@ -55,15 +55,6 @@ class SoCSDRAM(SoCCore):
 
 def soc_sdram_args(parser):
     soc_core_args(parser)
-    # L2 Cache
-    parser.add_argument("--l2-size", default=8192, type=auto_int,
-                        help="L2 cache size (default=8192)")
-    parser.add_argument("--min-l2-data-width", default=128, type=auto_int,
-                        help="Minimum L2 cache datawidth (default=128)")
-
-    # SDRAM
-    parser.add_argument("--max-sdram-size", default=0x40000000, type=auto_int,
-                        help="Maximum SDRAM size mapped to the SoC (default=1GB))")
 
 def soc_sdram_argdict(args):
     r = soc_core_argdict(args)
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index f56325634..2ce897f70 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -299,6 +299,12 @@ def soc_core_args(parser):
     parser.add_argument("--no-timer",        action="store_true", help="Disable Timer (default=False).")
     parser.add_argument("--timer-uptime",    action="store_true", help="Add an uptime capability to Timer (default=False).")
 
+    # L2 Cache
+    parser.add_argument("--l2-size",           default=8192, type=auto_int, help="L2 cache size (default=8192).")
+    parser.add_argument("--min-l2-data-width", default=128,  type=auto_int, help="Minimum L2 cache datawidth (default=128).")
+
+    # SDRAM
+    parser.add_argument("--max-sdram-size", default=0x40000000, type=auto_int, help="Maximum SDRAM size mapped to the SoC (default=1GB))")
 
 def soc_core_argdict(args):
     r = dict()