From 511832a911cbe3f36e78c97d5c642155fb2a74da Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 1 Jun 2020 10:58:45 +0200 Subject: [PATCH] soc/interconnect/axi: generate wishbone.sel for reads. --- litex/soc/interconnect/axi.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 2c444d60b..e95e01e03 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -365,6 +365,7 @@ class AXILite2Wishbone(Module): wishbone.stb.eq(1), wishbone.cyc.eq(1), wishbone.adr.eq(_r_addr[wishbone_adr_shift:]), + wishbone.sel.eq(2**len(wishbone.sel) - 1), If(wishbone.ack, axi_lite.ar.ready.eq(1), NextValue(_data, wishbone.dat_r),