From 518a6822d93e218404cf54405dd96a4163a8e7f9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 19 May 2014 12:03:26 +0200 Subject: [PATCH] mibuild/platforms: use add_period_constraint --- mibuild/platforms/de0nano.py | 8 +++++++- mibuild/platforms/lx9_microboard.py | 15 +++++---------- mibuild/platforms/m1.py | 21 ++++++--------------- mibuild/platforms/mixxeo.py | 21 ++++++--------------- mibuild/platforms/papilio_pro.py | 5 +---- mibuild/platforms/zedboard.py | 5 +---- mibuild/platforms/ztex_115d.py | 5 +---- 7 files changed, 27 insertions(+), 53 deletions(-) diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py index 6cd199f44..b0906528d 100644 --- a/mibuild/platforms/de0nano.py +++ b/mibuild/platforms/de0nano.py @@ -92,4 +92,10 @@ _io = [ class Platform(AlteraQuartusPlatform): def __init__(self): AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io, - lambda p: CRG_SE(p, "clk50", "key", 20.0, True)) + lambda p: CRG_SE(p, "clk50", None)) + + def do_finalize(self, fragment): + try: + self.add_period_constraint(self.lookup_request("clk50"), 20) + except ConstraintError: + pass diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py index 84ee5ae26..70072a06f 100644 --- a/mibuild/platforms/lx9_microboard.py +++ b/mibuild/platforms/lx9_microboard.py @@ -115,22 +115,17 @@ CONFIG VCCAUX = "3.3"; def do_finalize(self, fragment): try: - self.add_platform_command(""" -NET "{clk_y3}" TNM_NET = "GRPclky3"; -TIMESPEC "TSclky3" = PERIOD "GRPclky3" 10 ns HIGH 50%; -""", clk_y3=self.lookup_request("clk_y3")) + self.add_period_constraint(self.lookup_request("clk_y3"), 10) except ConstraintError: pass try: eth_clocks = self.lookup_request("eth_clocks") + self.add_period_constraint(eth_clocks.rx, 40) + self.add_period_constraint(eth_clocks.tx, 40) self.add_platform_command(""" -NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk"; -NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk"; -TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%; -TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%; -TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns; -TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; +TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns; +TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns; """, phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) except ContraintError: pass diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index ef89b4ed0..094659a13 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -123,22 +123,17 @@ class Platform(XilinxISEPlatform): def do_finalize(self, fragment): try: - self.add_platform_command(""" -NET "{clk50}" TNM_NET = "GRPclk50"; -TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%; -""", clk50=self.lookup_request("clk50")) + self.add_period_constraint(self.lookup_request("clk50"), 20) except ConstraintError: pass try: eth_clocks = self.lookup_request("eth_clocks") + self.add_period_constraint(eth_clocks.rx, 40) + self.add_period_constraint(eth_clocks.tx, 40) self.add_platform_command(""" -NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk"; -NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk"; -TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%; -TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%; -TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns; -TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; +TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns; +TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns; """, phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) except ConstraintError: pass @@ -146,10 +141,6 @@ TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; for i in range(2): si = "dviclk"+str(i) try: - self.add_platform_command(""" -NET "{dviclk}" TNM_NET = "GRP"""+si+""""; -NET "{dviclk}" CLOCK_DEDICATED_ROUTE = FALSE; -TIMESPEC "TS"""+si+"""" = PERIOD "GRP"""+si+"""" 26.7 ns HIGH 50%; -""", dviclk=self.lookup_request("dvi_in", i).clk) + self.add_period_constraint(self.lookup_request("dvi_in", i).clk, 26.7) except ConstraintError: pass diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index 12b242fb8..bdc80698a 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -160,32 +160,23 @@ class Platform(XilinxISEPlatform): def do_finalize(self, fragment): try: - self.add_platform_command(""" -NET "{clk50}" TNM_NET = "GRPclk50"; -TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%; -""", clk50=self.lookup_request("clk50")) + self.add_period_constraint(self.lookup_request("clk50"), 20) except ConstraintError: pass try: eth_clocks = self.lookup_request("eth_clocks") + self.add_period_constraint(eth_clocks.rx, 40) + self.add_period_constraint(eth_clocks.tx, 40) self.add_platform_command(""" -NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk"; -NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk"; -TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%; -TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%; -TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns; -TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; +TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns; +TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns; """, phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) except ConstraintError: pass for i in range(4): - si = "dviclk"+str(i) try: - self.add_platform_command(""" -NET "{dviclk}" TNM_NET = "GRP"""+si+""""; -TIMESPEC "TS"""+si+"""" = PERIOD "GRP"""+si+"""" 12.00 ns HIGH 50%; -""", dviclk=self.lookup_request("dvi_in", i).clk_p) + self.add_period_constraint(self.lookup_request("dvi_in", i).clk_p, 12) except ConstraintError: pass diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py index 876e995b6..9b20530bd 100644 --- a/mibuild/platforms/papilio_pro.py +++ b/mibuild/platforms/papilio_pro.py @@ -54,9 +54,6 @@ class Platform(XilinxISEPlatform): def do_finalize(self, fragment): try: - self.add_platform_command(""" -NET "{clk32}" TNM_NET = "GRPclk32"; -TIMESPEC "TSclk32" = PERIOD "GRPclk32" 31.25 ns HIGH 50%; -""", clk32=self.lookup_request("clk32")) + self.add_period_constraint(self.lookup_request("clk32"), 31.25) except ConstraintError: pass diff --git a/mibuild/platforms/zedboard.py b/mibuild/platforms/zedboard.py index 2d99fd0b6..8d6d7f3d5 100644 --- a/mibuild/platforms/zedboard.py +++ b/mibuild/platforms/zedboard.py @@ -143,9 +143,6 @@ class Platform(XilinxISEPlatform): def do_finalize(self, fragment): try: - self.add_platform_command(""" -NET "{clk100}" TNM_NET = "GRPclk100"; -TIMESPEC "TSclk100" = PERIOD "GRPclk100" 10 ns HIGH 50%; -""", clk100=self.lookup_request("clk100")) + self.add_period_constraint(self.lookup_request("clk100"), 10) except ConstraintError: pass diff --git a/mibuild/platforms/ztex_115d.py b/mibuild/platforms/ztex_115d.py index 8889b1d5a..ae488f8b0 100644 --- a/mibuild/platforms/ztex_115d.py +++ b/mibuild/platforms/ztex_115d.py @@ -90,10 +90,7 @@ CONFIG VCCAUX = "2.5"; def do_finalize(self, fragment): try: - self.add_platform_command(""" -NET "{clk_if}" TNM_NET = "GRPclkif"; -TIMESPEC "TSclkif" = PERIOD "GRPclkif" 20 ns HIGH 50%; -""", clk_if=self.lookup_request("clk_if")) + self.add_period_constraint(self.lookup_request("clk_if"), 20) except ConstraintError: pass