From 51f2e6ce6440cd870a7ce8d68b550c52d5e5e313 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 7 Jul 2020 12:11:47 +0200 Subject: [PATCH] build/io/InferedSDRTristate: pass clock domain to SDROutput/SDRInput. --- litex/build/io.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/build/io.py b/litex/build/io.py index f18f08ac2..42f9531ee 100644 --- a/litex/build/io.py +++ b/litex/build/io.py @@ -81,8 +81,8 @@ class InferedSDRTristate(Module): _o = Signal() _oe = Signal() _i = Signal() - self.specials += SDROutput(o, _o) - self.specials += SDRInput(_i, i) + self.specials += SDROutput(o, _o, clk) + self.specials += SDRInput(_i, i, clk) self.submodules += InferedSDRIO(oe, _oe, clk, clk_domain) self.specials += Tristate(io, _o, _oe, _i)