From 85e9881f45ff22876c9c6424760fcc164ecc7cce Mon Sep 17 00:00:00 2001
From: mohamedElbouazzati <elbouazzati.mohamed.2e@gmail.com>
Date: Wed, 19 Oct 2022 17:48:36 +0200
Subject: [PATCH] Fix IRQS for cv32e41p

---
 litex/soc/cores/cpu/cv32e41p/csr-defs.h | 14 ++++++++---
 litex/soc/cores/cpu/cv32e41p/irq.h      | 10 +++++---
 litex/soc/software/libbase/isr.c        | 33 -------------------------
 3 files changed, 18 insertions(+), 39 deletions(-)

diff --git a/litex/soc/cores/cpu/cv32e41p/csr-defs.h b/litex/soc/cores/cpu/cv32e41p/csr-defs.h
index d98e8dfb7..7738c5d94 100644
--- a/litex/soc/cores/cpu/cv32e41p/csr-defs.h
+++ b/litex/soc/cores/cpu/cv32e41p/csr-defs.h
@@ -1,11 +1,19 @@
 #ifndef CSR_DEFS__H
 #define CSR_DEFS__H
 
+
 #define CSR_MSTATUS_MIE 0x8
 
-#define CSR_IRQ_MASK 0xBC0
-#define CSR_IRQ_PENDING 0xFC0
-
+#define CSR_IRQ_MASK    0x344
+#define CSR_IRQ_PENDING 0x304
+#define FIRQ_OFFSET     16
 #define CSR_DCACHE_INFO 0xCC0
 
 #endif	/* CSR_DEFS__H */
+
+
+/*
+For CV32E41P from https://docs.openhwgroup.org/projects/openhw-group-cv32e41p/control_status_registers.html
+Machine Interrupt Pending Register (mip): CSR_IRQ_MASK: 0x344
+Machine Interrupt Enable Register (mie): CSR_IRQ_PENDING: 0x304
+*/
diff --git a/litex/soc/cores/cpu/cv32e41p/irq.h b/litex/soc/cores/cpu/cv32e41p/irq.h
index f1dd4c285..de2c0ef95 100644
--- a/litex/soc/cores/cpu/cv32e41p/irq.h
+++ b/litex/soc/cores/cpu/cv32e41p/irq.h
@@ -20,17 +20,21 @@ static inline void irq_setie(unsigned int ie)
 
 static inline unsigned int irq_getmask(void)
 {
-    return 0; // FIXME
+        unsigned int mask;
+	asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
+	return (mask >> FIRQ_OFFSET);
 }
 
 static inline void irq_setmask(unsigned int mask)
 {
-    // FIXME
+    	asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask << FIRQ_OFFSET));
 }
 
 static inline unsigned int irq_pending(void)
 {
-    return 0;// FIXME
+        unsigned int pending;
+	asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
+	return (pending >> FIRQ_OFFSET);
 }
 
 #ifdef __cplusplus
diff --git a/litex/soc/software/libbase/isr.c b/litex/soc/software/libbase/isr.c
index ffcd185b9..ac7a7920c 100644
--- a/litex/soc/software/libbase/isr.c
+++ b/litex/soc/software/libbase/isr.c
@@ -107,40 +107,7 @@ void isr(void)
 #endif
     }
 }
-#elif defined(__cv32e41p__)
 
-#define FIRQ_OFFSET 16
-#define IRQ_MASK 0x7FFFFFFF
-#define INVINST 2
-#define ECALL 11
-#define RISCV_TEST
-
-void isr(void)
-{
-    unsigned int cause = csrr(mcause) & IRQ_MASK;
-
-    if (csrr(mcause) & 0x80000000) {
-#ifndef UART_POLLING
-        if (cause == (UART_INTERRUPT+FIRQ_OFFSET)){
-            uart_isr();
-        }
-#endif
-    } else {
-#ifdef RISCV_TEST
-        int gp;
-        asm volatile ("mv %0, gp" : "=r"(gp));
-        printf("E %d\n", cause);
-        if (cause == INVINST) {
-            printf("Inv Instr\n");
-            for(;;);
-        }
-        if (cause == ECALL) {
-            printf("Ecall (gp: %d)\n", gp);
-            csrw(mepc, csrr(mepc)+4);
-        }
-#endif
-    }
-}
 #elif defined(__microwatt__)
 
 void isr(uint64_t vec)