diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
index 773b64505..3cafb4a59 100644
--- a/misoclib/mem/sdram/module.py
+++ b/misoclib/mem/sdram/module.py
@@ -80,7 +80,39 @@ class MT46V32M16(SDRAMModule):
 		SDRAMModule.__init__(self, clk_freq, self.geom_settings, self.timing_settings)
 
 # LPDDR
+class MT46H32M16(SDRAMModule):
+	geom_settings = {
+		"nbanks":	4,
+		"nrows":	8192,
+		"ncols":	1024
+	}
+	timing_settings = {
+		"tRP":		15,
+		"tRCD":		15,
+		"tWR":		15,
+		"tWTR":		2,
+		"tREFI":	64*1000*1000/8192,
+		"tRFC":		72
+	}
+	def __init__(self, clk_freq):
+		SDRAMModule.__init__(self, clk_freq, self.geom_settings, self.timing_settings)
 
 # DDR2
 
 # DDR3
+class MT8JTF12864(SDRAMModule):
+	geom_settings = {
+		"nbanks":	8,
+		"nrows":	65536,
+		"ncols":	1024
+	}
+	timing_settings = {
+		"tRP":		15,
+		"tRCD":		15,
+		"tWR":		15,
+		"tWTR":		2,
+		"tREFI":	7800,
+		"tRFC":		70
+	}
+	def __init__(self, clk_freq):
+		SDRAMModule.__init__(self, clk_freq, self.geom_settings, self.timing_settings)
diff --git a/targets/kc705.py b/targets/kc705.py
index 0006e5000..81eec083a 100644
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -2,6 +2,7 @@ from migen.fhdl.std import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoclib.mem import sdram
+from misoclib.mem.sdram.module import MT8JTF12864
 from misoclib.mem.sdram.phy import k7ddrphy
 from misoclib.mem.flash import spiflash
 from misoclib.soc import mem_decoder
@@ -83,26 +84,14 @@ class BaseSoC(SDRAMSoC):
 		self.submodules.crg = _CRG(platform)
 
 		if not self.with_main_ram:
-			sdram_geom_settings = sdram.GeomSettings(
-				bank_a=3,
-				row_a=16,
-				col_a=10
-			)
-			sdram_timing_settings = sdram.TimingSettings(
-				tRP=self.ns(15),
-				tRCD=self.ns(15),
-				tWR=self.ns(15),
-				tWTR=2,
-				tREFI=self.ns(7800, False),
-				tRFC=self.ns(70)
-			)
+			sdram_module = MT8JTF12864(self.clk_freq)
 			sdram_controller_settings = sdram.ControllerSettings(
 				req_queue_size=8,
 				read_time=32,
 				write_time=16
 			)
 			self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
-			self.register_sdram_phy(self.ddrphy, sdram_geom_settings, sdram_timing_settings,
+			self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings,
 				sdram_controller_settings)
 
 		spiflash_pads = platform.request("spiflash")
diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 57b4f9c17..159869924 100644
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -4,6 +4,7 @@ from migen.fhdl.std import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoclib.mem import sdram
+from misoclib.mem.sdram.module import MT46H32M16
 from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.flash import spiflash
 from misoclib.soc.sdram import SDRAMSoC
@@ -98,19 +99,7 @@ class BaseSoC(SDRAMSoC):
 		self.submodules.crg = _CRG(platform, clk_freq)
 
 		if not self.with_main_ram:
-			sdram_geom_settings = sdram.GeomSettings(
-				bank_a=2,
-				row_a=13,
-				col_a=10
-			)
-			sdram_timing_settings = sdram.TimingSettings(
-				tRP=self.ns(15),
-				tRCD=self.ns(15),
-				tWR=self.ns(15),
-				tWTR=2,
-				tREFI=self.ns(64*1000*1000/8192, False),
-				tRFC=self.ns(72)
-			)
+			sdram_module = MT46H32M16(self.clk_freq)
 			sdram_controller_settings = sdram.ControllerSettings(
 				req_queue_size=8,
 				read_time=32,
@@ -125,7 +114,7 @@ class BaseSoC(SDRAMSoC):
 			platform.add_platform_command("""
 	PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
 	""")
-			self.register_sdram_phy(self.ddrphy, sdram_geom_settings, sdram_timing_settings,
+			self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings,
 				sdram_controller_settings)
 
 		self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)