From 52f1c45407b8daafc854771cecffeb5615d7da96 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 4 Mar 2015 23:13:14 +0100 Subject: [PATCH] LiteXXX cores: fix test_reg.py --- misoclib/com/liteeth/example_designs/test/test_regs.py | 2 +- misoclib/mem/litesata/example_designs/test/test_regs.py | 2 +- misoclib/tools/litescope/example_designs/test/test_regs.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/misoclib/com/liteeth/example_designs/test/test_regs.py b/misoclib/com/liteeth/example_designs/test/test_regs.py index 6432242c5..3e41821fb 100644 --- a/misoclib/com/liteeth/example_designs/test/test_regs.py +++ b/misoclib/com/liteeth/example_designs/test/test_regs.py @@ -4,7 +4,7 @@ def main(wb): ### print("sysid : 0x{:04x}".format(regs.identifier_sysid.read())) print("revision : 0x{:04x}".format(regs.identifier_revision.read())) - print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000)) + print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000))) SRAM_BASE = 0x02000000 wb.write(SRAM_BASE, [i for i in range(64)]) print(wb.read(SRAM_BASE, 64)) diff --git a/misoclib/mem/litesata/example_designs/test/test_regs.py b/misoclib/mem/litesata/example_designs/test/test_regs.py index b416d677b..eb30efbfb 100644 --- a/misoclib/mem/litesata/example_designs/test/test_regs.py +++ b/misoclib/mem/litesata/example_designs/test/test_regs.py @@ -4,6 +4,6 @@ def main(wb): ### print("sysid : 0x{:04x}".format(regs.identifier_sysid.read())) print("revision : 0x{:04x}".format(regs.identifier_revision.read())) - print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000)) + print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000))) ### wb.close() diff --git a/misoclib/tools/litescope/example_designs/test/test_regs.py b/misoclib/tools/litescope/example_designs/test/test_regs.py index b416d677b..eb30efbfb 100644 --- a/misoclib/tools/litescope/example_designs/test/test_regs.py +++ b/misoclib/tools/litescope/example_designs/test/test_regs.py @@ -4,6 +4,6 @@ def main(wb): ### print("sysid : 0x{:04x}".format(regs.identifier_sysid.read())) print("revision : 0x{:04x}".format(regs.identifier_revision.read())) - print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000)) + print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000))) ### wb.close()