From 5397623a7a8c171498caa244d2243b54529b61d2 Mon Sep 17 00:00:00 2001 From: bunnie Date: Thu, 17 Nov 2022 03:31:07 +0800 Subject: [PATCH] FIXME: flip polarity of reverse for downconverter case Not sure what is driving this, but, empirically the bytes are being swapped on the read path. Unfortunately the stride converter only has the ability to swap both at the same time, not one or the other. Could be possible that maybe the solution is to write the data into the memory in reverse order of what is expected? not sure. --- litex/soc/interconnect/stream.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index f019b49a1..3ce9690fc 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -453,7 +453,7 @@ class _DownConverter(Module): # Data path cases = {} for i in range(ratio): - n = ratio-i-1 if reverse else i + n = ratio-i-1 if not reverse else i # FIXME: flipped polarity for AXI stream case. Need to figure out how to make more generic? cases[i] = source.data.eq(sink.data[n*nbits_to:(n+1)*nbits_to]) self.comb += Case(mux, cases).makedefault()