From 53a567daef000f2d2457375bf610239c442fbec1 Mon Sep 17 00:00:00 2001 From: bunnie Date: Sun, 19 Jul 2020 03:00:25 +0800 Subject: [PATCH] wire up missing register bits. Not sure how they went missing...but just noticed them. --- litex/soc/cores/i2s.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/cores/i2s.py b/litex/soc/cores/i2s.py index a5dde4ca5..784356839 100644 --- a/litex/soc/cores/i2s.py +++ b/litex/soc/cores/i2s.py @@ -283,10 +283,12 @@ class S7I2S(Module, AutoCSR, AutoDoc): o_WRERR = rx_wrerr, ) self.comb += [ # Wire up the status signals and interrupts + self.rx_stat.fields.overflow.eq(rx_wrerr), self.rx_stat.fields.underflow.eq(rx_rderr), self.rx_stat.fields.dataready.eq(rx_almostfull), self.rx_stat.fields.wrcount.eq(rx_wrcount), self.rx_stat.fields.rdcount.eq(rx_rdcount), + self.rx_stat.fields.empty.eq(rx_empty), self.ev.rx_ready.trigger.eq(rx_almostfull), self.ev.rx_error.trigger.eq(rx_wrerr | rx_rderr), ]