diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py index ca20f7ad5..d62c9ca85 100755 --- a/litex/build/xilinx/ise.py +++ b/litex/build/xilinx/ise.py @@ -205,12 +205,13 @@ bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit{fail_stmt} # constraints and other constraints otherwise it will be unable to trace # them through clock objects like DCM and PLL objects. - def add_period_constraint(self, platform, clk, period): + def add_period_constraint(self, platform, clk, period, keep=True): if clk is None: return if hasattr(clk, "p"): clk = clk.p - clk.attr.add("keep") + if keep: + clk.attr.add("keep") platform.add_platform_command( """ NET "{clk}" TNM_NET = "PRD{clk}";