From 54339a6d5b8ed0ca55b7f7c4207510665ded2ea0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 16 May 2014 11:46:33 +0200 Subject: [PATCH] gensdrphy: fix memtype and change phase shift in comments. --- misoclib/sdramphy/gensdrphy.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/misoclib/sdramphy/gensdrphy.py b/misoclib/sdramphy/gensdrphy.py index fbb5bd4eb..450e456e7 100644 --- a/misoclib/sdramphy/gensdrphy.py +++ b/misoclib/sdramphy/gensdrphy.py @@ -7,7 +7,7 @@ # The PHY needs 2 Clock domains: # - sys_clk : The System Clock domain # - sys_clk_ps : The System Clock domain with its phase shifted -# (-0.75ns on C4@100MHz) +# (-3ns on C4@100MHz) # # Assert dfi_wrdata_en and present the data # on dfi_wrdata_mask/dfi_wrdata in the same @@ -35,7 +35,7 @@ class GENSDRPHY(Module): d = flen(pads.dq) self.phy_settings = lasmicon.PhySettings( - memtype=memtype, + memtype="SDR", dfi_d=d, nphases=1, rdphase=0,