From 549d23e4f70d5dfc677dc2b9c11bc442c56bbf2b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 9 Jul 2024 10:04:03 +0200 Subject: [PATCH] build/efinix: Add default parameter values and fix other typos. --- litex/build/efinix/efinity.py | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/litex/build/efinix/efinity.py b/litex/build/efinix/efinity.py index eeb85e983..a7791bf96 100644 --- a/litex/build/efinix/efinity.py +++ b/litex/build/efinix/efinity.py @@ -51,22 +51,22 @@ class EfinityToolchain(GenericToolchain): self.options["includ_path"] = "{" + ";".join(self.platform.verilog_include_paths) + "}" def build(self, platform, fragment, - synth_mode, - infer_clk_enable, - bram_output_regs_packing, - retiming, - seq_opt, - mult_input_regs_packing, - mult_output_regs_packing, + synth_mode = "speed", + infer_clk_enable = "3", + bram_output_regs_packing = "1", + retiming = "1", + seq_opt = "1", + mult_input_regs_packing = "1", + mult_output_regs_packing = "1", **kwargs): - self._synth_mode = synth_mode, - self._infer_clk_enable = infer_clk_enable, - self._bram_output_regs_packing = bram_output_regs_packing, - self._retiming = retiming, - self._seq_opt = seq_opt, - self._mult_input_regs_packing = mult_input_regs_packing, - self._mult_output_regs_packing = mult_output_regs_packing, + self._synth_mode = synth_mode + self._infer_clk_enable = infer_clk_enable + self._bram_output_regs_packing = bram_output_regs_packing + self._retiming = retiming + self._seq_opt = seq_opt + self._mult_input_regs_packing = mult_input_regs_packing + self._mult_output_regs_packing = mult_output_regs_packing # Apply FullMemoryWE on Design (Efiniy does not infer memories correctly otherwise). FullMemoryWE()(fragment)