diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index b789102f0..af556ce71 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -793,7 +793,7 @@ class AXILite2CSR(Module):
 # AXILite SRAM -------------------------------------------------------------------------------------
 
 class AXILiteSRAM(Module):
-    def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
+    def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=False):
         if bus is None:
             bus = AXILiteInterface()
         self.bus = bus
diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index d08e97ee6..f8db5e53c 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -330,7 +330,7 @@ class Converter(Module):
 # Wishbone SRAM ------------------------------------------------------------------------------------
 
 class SRAM(Module):
-    def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=True):
+    def __init__(self, mem_or_size, read_only=None, init=None, bus=None, burst=False):
         if bus is None:
             bus = Interface()
         self.bus = bus