From 54f8d90d38a19c416f87ec380b7ca630ea430a7c Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 7 Mar 2024 09:00:32 +0100 Subject: [PATCH] soc/cores/cpu/rocket/core: align config (XCACHE, XTLB) to pythondata-cpu-rocket master --- litex/soc/cores/cpu/rocket/core.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index d7b83fbe0..16d9ffdcd 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -340,20 +340,20 @@ class Rocket(CPU): soc.add_config("CPU_MMU", "sv39") # Constants for Cache so we can add them in the DTS. - soc.add_config("CPU_DCACHE_SIZE", 4096) # CHECKME: correct/hardwired? - soc.add_config("CPU_DCACHE_WAYS", 2) # CHECKME: correct/hardwired? + soc.add_config("CPU_DCACHE_SIZE", 16384) # CHECKME: correct/hardwired? + soc.add_config("CPU_DCACHE_WAYS", 64) # CHECKME: correct/hardwired? soc.add_config("CPU_DCACHE_BLOCK_SIZE", 64) # CHECKME: correct/hardwired? - soc.add_config("CPU_ICACHE_SIZE", 4096) # CHECKME: correct/hardwired? - soc.add_config("CPU_ICACHE_WAYS", 2) # CHECKME: correct/hardwired? + soc.add_config("CPU_ICACHE_SIZE", 16384) # CHECKME: correct/hardwired? + soc.add_config("CPU_ICACHE_WAYS", 64) # CHECKME: correct/hardwired? soc.add_config("CPU_ICACHE_BLOCK_SIZE", 64) # CHECKME: correct/hardwired? # Constants for TLB so we can add them in the DTS. - soc.add_config("CPU_DTLB_SIZE", 4) # CHECKME: correct/hardwired? - soc.add_config("CPU_DTLB_WAYS", 1) # CHECKME: correct/hardwired? + soc.add_config("CPU_DTLB_SIZE", 32) # CHECKME: correct/hardwired? + soc.add_config("CPU_DTLB_WAYS", 1) # CHECKME: correct/hardwired? - soc.add_config("CPU_ITLB_SIZE", 4) # CHECKME: correct/hardwired? - soc.add_config("CPU_ITLB_WAYS", 1) # CHECKME: correct/hardwired? + soc.add_config("CPU_ITLB_SIZE", 32) # CHECKME: correct/hardwired? + soc.add_config("CPU_ITLB_WAYS", 1) # CHECKME: correct/hardwired? def do_finalize(self): assert hasattr(self, "reset_address")