From 552b0243b398502d6140715139c1739227851b0f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 27 Mar 2019 21:15:14 +0100 Subject: [PATCH] soc/interconnect/axi: remove dead code (thanks gsomlo) --- litex/soc/interconnect/axi.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 7d0792cee..a110c36d2 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -78,8 +78,6 @@ class AXI2Wishbone(Module): NextState("DO-WRITE") ) ) - axi_ar_addr = Signal(32) - self.comb += axi_ar_addr.eq(axi.ar.addr - base_address) fsm.act("DO-READ", wishbone.stb.eq(1), wishbone.cyc.eq(1),