diff --git a/litex/soc/cores/clock/xilinx_common.py b/litex/soc/cores/clock/xilinx_common.py
index 4f7a62221..fdccb7864 100644
--- a/litex/soc/cores/clock/xilinx_common.py
+++ b/litex/soc/cores/clock/xilinx_common.py
@@ -22,6 +22,7 @@ class XilinxClocking(Module, AutoCSR):
     def __init__(self, vco_margin=0):
         self.vco_margin = vco_margin
         self.reset      = Signal()
+        self.power_down = Signal()
         self.locked     = Signal()
         self.clkin_freq = None
         self.vcxo_freq  = None
diff --git a/litex/soc/cores/clock/xilinx_s6.py b/litex/soc/cores/clock/xilinx_s6.py
index e64a48fa8..b44ff14ee 100644
--- a/litex/soc/cores/clock/xilinx_s6.py
+++ b/litex/soc/cores/clock/xilinx_s6.py
@@ -37,6 +37,7 @@ class S6PLL(XilinxClocking):
             p_BANDWIDTH      = "OPTIMIZED",
             p_COMPENSATION   = "INTERNAL",
             i_RST            = self.reset,
+            i_PWRDWN         = self.power_down,
             o_LOCKED         = self.locked,
 
             # VCO.
diff --git a/litex/soc/cores/clock/xilinx_s7.py b/litex/soc/cores/clock/xilinx_s7.py
index 3600e7fff..86d6ca0e6 100644
--- a/litex/soc/cores/clock/xilinx_s7.py
+++ b/litex/soc/cores/clock/xilinx_s7.py
@@ -34,6 +34,7 @@ class S7PLL(XilinxClocking):
             # Global.
             p_STARTUP_WAIT = "FALSE",
             i_RST          = self.reset,
+            i_PWRDWN       = self.power_down,
             o_LOCKED       = self.locked,
 
             # VCO.
@@ -81,6 +82,7 @@ class S7MMCM(XilinxClocking):
             # Global.
             p_BANDWIDTH = "OPTIMIZED",
             i_RST       = self.reset,
+            i_PWRDWN    = self.power_down,
             o_LOCKED    = self.locked,
 
             # VCO.
diff --git a/litex/soc/cores/clock/xilinx_us.py b/litex/soc/cores/clock/xilinx_us.py
index ffbe9b80e..34666c1ca 100644
--- a/litex/soc/cores/clock/xilinx_us.py
+++ b/litex/soc/cores/clock/xilinx_us.py
@@ -39,6 +39,7 @@ class USPLL(XilinxClocking):
             # Global.
             p_STARTUP_WAIT = "FALSE",
             i_RST          = self.reset,
+            i_PWRDWN       = self.power_down,
             o_LOCKED       = self.locked,
 
             # VCO.
@@ -84,6 +85,7 @@ class USMMCM(XilinxClocking):
             # Global.
             p_BANDWIDTH = "OPTIMIZED",
             i_RST       = self.reset,
+            i_PWRDWN    = self.power_down,
             o_LOCKED    = self.locked,
 
             # VCO.
diff --git a/litex/soc/cores/clock/xilinx_usp.py b/litex/soc/cores/clock/xilinx_usp.py
index 92e236e13..6e3c689a1 100644
--- a/litex/soc/cores/clock/xilinx_usp.py
+++ b/litex/soc/cores/clock/xilinx_usp.py
@@ -39,6 +39,7 @@ class USPPLL(XilinxClocking):
             # Global.
             p_STARTUP_WAIT = "FALSE",
             i_RST          = self.reset,
+            i_PWRDWN       = self.power_down,
             o_LOCKED       = self.locked,
 
             # VCO.
@@ -84,6 +85,7 @@ class USPMMCM(XilinxClocking):
             # Global.
             p_BANDWIDTH = "OPTIMIZED",
             i_RST       = self.reset,
+            i_PWRDWN    = self.power_down,
             o_LOCKED    = self.locked,
 
             # VCO.