From 555f89c22acffde45f363facf02e024dd9b2a87f Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 8 Apr 2024 17:16:15 +0200 Subject: [PATCH] set default l2 ways to 4 --- litex/soc/cores/cpu/vexiiriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index bbbbbfa04..1d86cbb95 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -50,7 +50,7 @@ class VexiiRiscv(CPU): internal_bus_width = 32 litedram_width = 32 l2_bytes = 0 - l2_ways = 0 + l2_ways = 4 with_fpu = False with_rvc = False with_rvm = False