From 55a790308fd1085e0856e0f9611ac5a7859eade0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 4 Feb 2022 09:01:00 +0100 Subject: [PATCH] cores/bitbang: Add TODO. --- CHANGES | 2 +- litex/soc/cores/bitbang.py | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/CHANGES b/CHANGES index ef9cf271b..aa507de2f 100644 --- a/CHANGES +++ b/CHANGES @@ -13,7 +13,7 @@ - openocd/stream: Simplify ECP5 JTAG-UART/JTAGBone use. - tools/litex_cli: Allow passing reg name to --read/--write. - soc/add_spi_sdcard: Allow optional Tristate (useful on ULX3S). - - software/bios: Add new mem_cmd memory comparison commmand. + - software/bios: Add new mem_cmd memory comparison command. - cpu/rocket: Increase IRQ lines to 8. - cpu/serv: Add MDU support. - cpu/marocchino: Add initial support. diff --git a/litex/soc/cores/bitbang.py b/litex/soc/cores/bitbang.py index 577933395..8453c90f7 100644 --- a/litex/soc/cores/bitbang.py +++ b/litex/soc/cores/bitbang.py @@ -85,6 +85,8 @@ class I2CMasterSim(I2CMaster): # I2C Master Info Collection ---------------------------------------------------------------------- +# TODO: Find a more generic way to do it that would also apply to other peripherals? + def collect_i2c_info(soc): i2c_init = [] i2c_devs = []