From 571ce5791a68e525711ed921cfc773c5879bf2e1 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 10 Jun 2015 12:14:48 +0200
Subject: [PATCH] litesata/phy/k7: apply AR# 63869 to keep CDR in hold during
 SATA link initialization

self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.
---
 misoclib/mem/litesata/phy/k7/trx.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/misoclib/mem/litesata/phy/k7/trx.py b/misoclib/mem/litesata/phy/k7/trx.py
index 1ca9c9f47..e22982844 100644
--- a/misoclib/mem/litesata/phy/k7/trx.py
+++ b/misoclib/mem/litesata/phy/k7/trx.py
@@ -575,7 +575,7 @@ class K7LiteSATAPHYTRX(Module):
 
                 # Receive Ports - CDR Ports
                     i_RXCDRFREQRESET=0,
-                    i_RXCDRHOLD=0,
+                    i_RXCDRHOLD=self.rxelecidle,
                     #o_RXCDRLOCK=,
                     i_RXCDROVRDEN=0,
                     i_RXCDRRESET=0,