From 573479b395e6cf3082f0798c732feb63fb7346ff Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 20 Jun 2022 19:07:27 +0200
Subject: [PATCH] interconnect:axi/axi_lite/interconnect: Cosmetic cleanups.

---
 litex/soc/interconnect/axi/axi_lite.py | 45 ++++++++++++++++----------
 1 file changed, 28 insertions(+), 17 deletions(-)

diff --git a/litex/soc/interconnect/axi/axi_lite.py b/litex/soc/interconnect/axi/axi_lite.py
index 3fb7a763c..763f40d9e 100644
--- a/litex/soc/interconnect/axi/axi_lite.py
+++ b/litex/soc/interconnect/axi/axi_lite.py
@@ -568,7 +568,7 @@ class AXILiteTimeout(Module):
                 )
             ])
 
-# AXI-Lite Interconnect ----------------------------------------------------------------------------
+# AXI-Lite Interconnect Components -----------------------------------------------------------------
 
 class _AXILiteRequestCounter(Module):
     def __init__(self, request, response, max_requests=256):
@@ -594,10 +594,6 @@ class _AXILiteRequestCounter(Module):
             ),
         ]
 
-class AXILiteInterconnectPointToPoint(Module):
-    def __init__(self, master, slave):
-        self.comb += master.connect(slave)
-
 class AXILiteArbiter(Module):
     """AXI Lite arbiter
 
@@ -633,9 +629,13 @@ class AXILiteArbiter(Module):
 
         # Allow to change rr.grant only after all requests from a master have been responded to.
         self.submodules.wr_lock = wr_lock = _AXILiteRequestCounter(
-            request=target.aw.valid & target.aw.ready, response=target.b.valid & target.b.ready)
+            request  = target.aw.valid & target.aw.ready,
+            response = target.b.valid  & target.b.ready
+        )
         self.submodules.rd_lock = rd_lock = _AXILiteRequestCounter(
-            request=target.ar.valid & target.ar.ready, response=target.r.valid & target.r.ready)
+            request  = target.ar.valid & target.ar.ready,
+            response = target.r.valid  & target.r.ready
+        )
 
         # Switch to next request only if there are no responses pending.
         self.comb += [
@@ -681,11 +681,13 @@ class AXILiteDecoder(Module):
         # TODO: we could reuse arbiter counters
         locks = {
             "write": _AXILiteRequestCounter(
-                request=master.aw.valid & master.aw.ready,
-                response=master.b.valid & master.b.ready),
+                request  = master.aw.valid & master.aw.ready,
+                response = master.b.valid & master.b.ready,
+            ),
             "read": _AXILiteRequestCounter(
-                request=master.ar.valid & master.ar.ready,
-                response=master.r.valid & master.r.ready),
+                request  = master.ar.valid & master.ar.ready,
+                response = master.r.valid & master.r.ready
+            ),
         }
         self.submodules += locks.values()
 
@@ -701,16 +703,18 @@ class AXILiteDecoder(Module):
                 slave_sel_dec["read"][i].eq(decoder(master.ar.addr[addr_shift:])),
             ]
 
-        # Dhange the current selection only when we've got all responses.
+        # Change the current selection only when we've got all responses.
         for channel in locks.keys():
             self.sync += If(locks[channel].ready, slave_sel_reg[channel].eq(slave_sel_dec[channel]))
         # We have to cut the delaying select.
         for ch, final in slave_sel.items():
-            self.comb += If(locks[ch].ready,
-                             final.eq(slave_sel_dec[ch])
-                         ).Else(
-                             final.eq(slave_sel_reg[ch])
-                         )
+            self.comb += [
+                If(locks[ch].ready,
+                    final.eq(slave_sel_dec[ch])
+                ).Else(
+                    final.eq(slave_sel_reg[ch])
+                )
+            ]
 
         # Connect master->slaves signals except valid/ready.
         for i, (_, slave) in enumerate(slaves):
@@ -735,6 +739,13 @@ class AXILiteDecoder(Module):
                     masked.append(src & mask)
                 self.comb += dst.eq(reduce(or_, masked))
 
+# AXI-Lite Interconnect ----------------------------------------------------------------------------
+
+class AXILiteInterconnectPointToPoint(Module):
+    """AXI Lite point to point interconnect"""
+    def __init__(self, master, slave):
+        self.comb += master.connect(slave)
+
 class AXILiteInterconnectShared(Module):
     """AXI Lite shared interconnect"""
     def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):