From 57576fa8fccf64929d15c1a98bb496a7e77dae7d Mon Sep 17 00:00:00 2001
From: Piotr Esden-Tempski <piotr@esden.net>
Date: Fri, 13 Mar 2020 14:24:27 -0700
Subject: [PATCH] Add bit more logic to decide when to switch to multilane CSR
 documentation.

Now we only generate multilane bitfield documentation when the CSR has
fields, and the smallest field is less than 8bit long. As this is when
we start running into space problems with the field names.
---
 litex/soc/doc/csr.py | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/litex/soc/doc/csr.py b/litex/soc/doc/csr.py
index 0b0670daa..cfc17bf6d 100644
--- a/litex/soc/doc/csr.py
+++ b/litex/soc/doc/csr.py
@@ -235,7 +235,9 @@ class DocumentedCSRRegion:
         print("", file=stream)
         print("        {", file=stream)
         print("            \"reg\": [", file=stream)
+        multilane = False
         if len(reg.fields) > 0:
+            min_field_size = self.csr_data_width
             bit_offset = 0
             for field in reg.fields:
                 field_name = field.name
@@ -254,6 +256,9 @@ class DocumentedCSRRegion:
                     term=""
                 print("                {\"name\": \"" + field_name + "\",  " + type_str + attr_str + "\"bits\": " + str(field.size) + "}" + term, file=stream)
                 bit_offset = field.offset + field.size
+                min_field_size = min(min_field_size, field.size)
+                if min_field_size < 8:
+                    multilane = True
             if bit_offset != self.busword:
                 print("                {\"bits\": " + str(self.busword - bit_offset) + "}", file=stream)
         else:
@@ -265,8 +270,12 @@ class DocumentedCSRRegion:
                 attr_str = "\"attr\": 'reset: " + str(reg.reset_value) + "', "
             print("                {\"name\": \"" + reg.short_name.lower() + self.bit_range(reg.offset, reg.offset + reg.size, empty_if_zero=True) + "\", " + attr_str + "\"bits\": " + str(reg.size) + "}" + term, file=stream)
             if reg.size != self.csr_data_width:
+                multilane = True
                 print("                {\"bits\": " + str(self.csr_data_width - reg.size) + "},", file=stream)
-        lanes = self.busword / 8
+        if multilane:
+            lanes = self.busword / 8
+        else:
+            lanes = 1
         print("            ], \"config\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": " + str(lanes) + " }, \"options\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": " + str(lanes) + "}", file=stream)
         print("        }", file=stream)
         print("", file=stream)