diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index 76ebeb116..76f64a8cb 100644
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -1,10 +1,14 @@
 #
 # This file is part of LiteX.
 #
-# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2015-2022 Florent Kermarrec <florent@enjoy-digital.fr>
 # Copyright (c) 2017-2018 Tim 'mithro' Ansell <me@mith.ro>
 # SPDX-License-Identifier: BSD-2-Clause
 
+import os
+import inspect
+import importlib
+
 from migen import *
 
 # CPU ----------------------------------------------------------------------------------------------
@@ -30,14 +34,14 @@ class CPU(Module):
         pass
 
 class CPUNone(CPU):
-    variants             = ["standard"]
-    data_width           = 32
-    endianness           = "little"
-    reset_address        = 0x00000000
-    io_regions           = {0x00000000: 0x100000000} # origin, length
-    periph_buses         = []
-    memory_buses         = []
-    mem_map              = {
+    variants      = ["standard"]
+    data_width    = 32
+    endianness    = "little"
+    reset_address = 0x00000000
+    io_regions    = {0x00000000: 0x100000000} # origin, length
+    periph_buses  = []
+    memory_buses  = []
+    mem_map       = {
         "csr"      : 0x00000000,
         "ethmac"   : 0x00020000, # FIXME: Remove.
         "spiflash" : 0x10000000, # FIXME: Remove.
@@ -70,76 +74,36 @@ CPU_GCC_TRIPLE_RISCV64 = (
 
 # CPUS ---------------------------------------------------------------------------------------------
 
-# LM32
-from litex.soc.cores.cpu.lm32 import LM32
+def collect_cpus():
+    cpus = {
+        # None.
+        "None"     : CPUNone,
+        # External (CPU class provided externally by design/user)
+        "external" : None,
+    }
+    path = os.path.dirname(__file__)
 
-# OpenRisc
-from litex.soc.cores.cpu.mor1kx import MOR1KX
-from litex.soc.cores.cpu.marocchino import Marocchino
+    # Search for CPUs in cpu directory.
+    for file in os.listdir(path):
 
-# OpenPower
-from litex.soc.cores.cpu.microwatt import Microwatt
+        # Verify that it's a path...
+        cpu_path = os.path.join(os.path.dirname(__file__), file)
+        if not os.path.isdir(cpu_path):
+            continue
 
-# RISC-V (32-bit)
-from litex.soc.cores.cpu.serv import SERV
-from litex.soc.cores.cpu.femtorv import FemtoRV
-from litex.soc.cores.cpu.picorv32 import PicoRV32
-from litex.soc.cores.cpu.minerva import Minerva
-from litex.soc.cores.cpu.vexriscv import VexRiscv
-from litex.soc.cores.cpu.vexriscv_smp import VexRiscvSMP
-from litex.soc.cores.cpu.ibex import Ibex
-from litex.soc.cores.cpu.cv32e40p import CV32E40P
+        # ... and that core.py is present.
+        cpu_core = os.path.join(cpu_path, "core.py")
+        if not os.path.exists(cpu_core):
+            continue
 
-# RISC-V (64-bit)
-from litex.soc.cores.cpu.rocket import RocketRV64
-from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
+        # OK, it seems to be a CPU; now get the class and add it to dict.
+        cpu        = file
+        cpu_module = f"litex.soc.cores.cpu.{cpu}.core"
+        for cpu_name, cpu_cls in inspect.getmembers(importlib.import_module(cpu_module), inspect.isclass):
+            if cpu.replace("_", "") == cpu_name.lower():
+                cpus[cpu] = cpu_cls
 
-# Zynq
-from litex.soc.cores.cpu.zynq7000 import Zynq7000
+    # Return collected CPUs.
+    return cpus
 
-# EOS-S3
-from litex.soc.cores.cpu.eos_s3 import EOS_S3
-
-# Gowin EMCU
-from litex.soc.cores.cpu.gowin_emcu import GowinEMCU
-
-CPUS = {
-    # None
-    "None"        : CPUNone,
-
-    # External (CPU class provided externally by design/user)
-    "external"    : None,
-
-    # LM32
-    "lm32"        : LM32,
-
-    # OpenRisc
-    "mor1kx"      : MOR1KX,
-    "marocchino"  : Marocchino,
-
-    # OpenPower
-    "microwatt"   : Microwatt,
-
-    # RISC-V (32-bit)
-    "serv"        : SERV,
-    "femtorv"     : FemtoRV,
-    "picorv32"    : PicoRV32,
-    "minerva"     : Minerva,
-    "vexriscv"    : VexRiscv,
-    "vexriscv_smp": VexRiscvSMP,
-    "ibex"        : Ibex,
-    "cv32e40p"    : CV32E40P,
-
-    # RISC-V (64-bit)
-    "rocket"      : RocketRV64,
-    "blackparrot" : BlackParrotRV64,
-
-    # Zynq
-    "zynq7000"    : Zynq7000,
-
-    # EOS-S3
-    "eos_s3"      : EOS_S3,
-
-    # Gowin EMCU
-    'gowin_emcu'  : GowinEMCU
-}
+CPUS = collect_cpus()