diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 11f8142e9..fee8de48c 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1804,6 +1804,8 @@ class LiteXSoC(SoC):
             interface   = interface,
             endianness  = endianness,
         )
+        if interface == "hybrid":
+            ethcore.autocsr_exclude = {"mac"} # Exclude MAC here since added externally.
         if not with_sys_datapath:
             # Use PHY's eth_tx/eth_rx clock domains.
             ethcore = ClockDomainsRenamer({