From 57840c63a31602f15b03f3b7918a853c951fc9e1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 13 Jun 2023 13:23:47 +0200 Subject: [PATCH] cores/clock/xilinx_common: Add BUFH support and lower buf parameter before use to allow user to specify it in upper or lower case. --- litex/soc/cores/clock/xilinx_common.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex/soc/cores/clock/xilinx_common.py b/litex/soc/cores/clock/xilinx_common.py index 02b9d9f46..e79ed45ae 100644 --- a/litex/soc/cores/clock/xilinx_common.py +++ b/litex/soc/cores/clock/xilinx_common.py @@ -53,10 +53,13 @@ class XilinxClocking(Module, AutoCSR): else: clkout_buf = Signal() self.comb += cd.clk.eq(clkout_buf) + buf = buf.lower() if buf == "bufg": self.specials += Instance("BUFG", i_I=clkout, o_O=clkout_buf) elif buf == "bufr": self.specials += Instance("BUFR", i_I=clkout, o_O=clkout_buf) + elif buf == "bufh": + self.specials += Instance("BUFH", i_I=clkout, o_O=clkout_buf) elif buf == "bufgce": if ce is None: raise ValueError("BUFGCE requires user to provide a clock enable ce Signal")