From 18e90234b0857af5ac564b0e6dedfe72b6df73bb Mon Sep 17 00:00:00 2001
From: Piotr Binkowski <pbinkowski@antmicro.com>
Date: Tue, 15 Dec 2020 17:22:44 +0100
Subject: [PATCH 1/2] interconnect/axi: add get_ios to full AXI

---
 litex/soc/interconnect/axi.py | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index af73a97d9..29ab122c8 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -142,6 +142,19 @@ class AXIInterface:
     def connect_to_pads(self, pads, mode="master"):
         return connect_to_pads(self, pads, mode)
 
+    def get_ios(self, bus_name="wb"):
+        subsignals = []
+        for channel in ["aw", "w", "b", "ar", "r"]:
+            for name in ["valid", "ready"]:
+                subsignals.append(Subsignal(channel + name, Pins(1)))
+            for name, width in getattr(self, channel).description.payload_layout:
+                subsignals.append(Subsignal(channel + name, Pins(width)))
+
+        subsignals.append(Subsignal("rlast", Pins(1)))
+        subsignals.append(Subsignal("wlast", Pins(1)))
+        ios = [(bus_name , 0) + tuple(subsignals)]
+        return ios
+
     def connect(self, slave, **kwargs):
         return _connect_axi(self, slave, **kwargs)
 

From f26769eb4da141226b44cc68e58dd707cb029907 Mon Sep 17 00:00:00 2001
From: Piotr Binkowski <pbinkowski@antmicro.com>
Date: Wed, 16 Dec 2020 17:30:04 +0100
Subject: [PATCH 2/2] interconnect/axi: add connect_to_pads to full AXI

---
 litex/soc/interconnect/axi.py | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 29ab122c8..99b377db1 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -140,7 +140,16 @@ class AXIInterface:
         self.r  = stream.Endpoint(r_description(data_width, id_width))
 
     def connect_to_pads(self, pads, mode="master"):
-        return connect_to_pads(self, pads, mode)
+        r = connect_to_pads(self, pads, mode)
+
+        if mode == "master":
+            r.append(pads.wlast.eq(self.w.last))
+            r.append(self.r.last.eq(pads.rlast))
+        else:
+            r.append(pads.rlast.eq(self.r.last))
+            r.append(self.w.last.eq(pads.wlast))
+
+        return r
 
     def get_ios(self, bus_name="wb"):
         subsignals = []