From 57faa9102f3de89c0be83e37e070cd8de364e861 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 Sep 2023 12:40:03 +0200
Subject: [PATCH] CHANGES: Update.

---
 CHANGES.md | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/CHANGES.md b/CHANGES.md
index 6ce9e8dda..0072e94d1 100644
--- a/CHANGES.md
+++ b/CHANGES.md
@@ -61,6 +61,9 @@
 	- soc/interconnect/stream      : Added pipe_valid/pipe_ready parameters to BufferizeEndpoints.
 	- soc/cores/clock              : Added initial GW5A support.
 	- build/efinix                 : Added initial EfinixDDROutput/Input and simplified IOs exclusion.
+	- soc/interconnect             : Improved DMA Bus to use the same Bus Standard than the CPU DMA Bus.
+	- liteeth/phy                  : Added Artix7 2500BASE-X PHY.
+	- liteeth/phy                  : Added Gowin Arora V RGMII PHY (GW5RGMII).
 
 	[> Changed
 	----------