From e4ceaa7cc2dfc0b68bad4e59d44604671c2efcd4 Mon Sep 17 00:00:00 2001 From: Michael Betz Date: Sat, 22 Jan 2022 13:00:53 +0100 Subject: [PATCH] bitbang.py: initialize SCL / SDA lines to high on reset * otherwise might block the I2C bus on reset --- litex/soc/cores/bitbang.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/bitbang.py b/litex/soc/cores/bitbang.py index 5a52d54f8..325c6d475 100644 --- a/litex/soc/cores/bitbang.py +++ b/litex/soc/cores/bitbang.py @@ -28,9 +28,9 @@ class I2CMaster(Module, AutoCSR): pads = Record(self.pads_layout) self.pads = pads self._w = CSRStorage(fields=[ - CSRField("scl", size=1, offset=0), + CSRField("scl", size=1, offset=0, reset=1), CSRField("oe", size=1, offset=1), - CSRField("sda", size=1, offset=2)], + CSRField("sda", size=1, offset=2, reset=1)], name="w") self._r = CSRStatus(fields=[ CSRField("sda", size=1, offset=0)],