From 584fd51c01f5ce9f8b5aa79db6472dec72527aa6 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 12 Dec 2018 09:37:24 +0100
Subject: [PATCH] build/sim/verilator: add support for plaform.sources, some
 cleanup

---
 litex/build/sim/core/Makefile |  4 +++-
 litex/build/sim/verilator.py  | 39 +++++++++++++++++++++--------------
 2 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile
index 80d201e3e..3a6121247 100644
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@@ -4,6 +4,8 @@ CC = gcc
 CFLAGS = -Wall -O3 -ggdb
 LDFLAGS = -lpthread -ljson-c -lm -lstdc++ -ldl -levent
 
+CC_SRCS ?= "--cc dut.v"
+
 SRC_DIR ?= .
 INC_DIR ?= .
 MOD_DIR = $(SRC_DIR)/modules
@@ -24,7 +26,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c
 
 .PHONY: sim
 sim: mkdir $(OBJS_SIM)
-	verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \
+	verilator -Wno-fatal -O3 $(CC_SRCS) --top-module dut --exe \
 		$(SRCS_SIM_CPP) $(OBJS_SIM) \
 		--top-module dut \
 		$(if $(THREADS), --threads $(THREADS),) \
diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 397003298..0d3c63f2e 100644
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -1,4 +1,4 @@
-# This file is Copyright (c) 2015-2016 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
 #                            2017 Pierre-Olivier Vauboin <po@lambdaconcept.com>
 # License: BSD
 
@@ -105,7 +105,6 @@ def _generate_sim_variables(include_paths):
     include = ""
     for path in include_paths:
         include += "-I"+path+" "
-
     content = """\
 SRC_DIR = {}
 INC_DIR = {}
@@ -118,13 +117,17 @@ def _generate_sim_config(config):
     tools.write_to_file("sim_config.js", content)
 
 
-def _build_sim(platform, build_name, threads, coverage, verbose):
+def _build_sim(platform, build_name, sources, threads, coverage, verbose):
     makefile = os.path.join(core_directory, 'Makefile')
+    cc_srcs = []
+    for filename, language, library in sources:
+        cc_srcs.append("--cc " + filename + " ")
     build_script_contents = """\
 rm -rf obj_dir/
-make -C . -f {} {} {}
+make -C . -f {} {} {} {}
 mkdir -p modules && cp obj_dir/*.so modules
 """.format(makefile,
+    "CC_SRCS=\"{}\"".format("".join(cc_srcs)),
     "THREADS={}".format(threads) if int(threads) > 1 else "",
     "COVERAGE=1" if coverage else "",
     )
@@ -166,37 +169,41 @@ class SimVerilatorToolchain:
             toolchain_path=None, serial="console", build=True, run=True, threads=1,
             verbose=True, sim_config=None, trace=False, coverage=False):
 
+        # create build directory
         os.makedirs(build_dir, exist_ok=True)
         os.chdir(build_dir)
 
         if build:
+            # finalize design
             if not isinstance(fragment, _Fragment):
                 fragment = fragment.get_fragment()
             platform.finalize(fragment)
 
-            v_output = platform.get_verilog(fragment,
+            # generate top module
+            top_output = platform.get_verilog(fragment,
                 name=build_name, dummy_signal=False, regular_comb=False, blocking_assign=True)
-            named_sc, named_pc = platform.resolve_signals(v_output.ns)
-            v_output.write(build_name + ".v")
+            named_sc, named_pc = platform.resolve_signals(top_output.ns)
+            top_file = build_name + ".v"
+            top_output.write(top_file)
+            platform.add_source(top_file)
 
-            include_paths = []
-            for source in platform.sources:
-                path = os.path.dirname(source[0]).replace("\\", "\/")
-                if path not in include_paths:
-                    include_paths.append(path)
-            include_paths += platform.verilog_include_paths
+            # generate cpp header/main/variables
             _generate_sim_h(platform)
             _generate_sim_cpp(platform, trace)
-            _generate_sim_variables(include_paths)
+            _generate_sim_variables(platform.verilog_include_paths)
+
+            # generate sim config
             if sim_config:
                 _generate_sim_config(sim_config)
 
-            _build_sim(platform, build_name, threads, coverage, verbose)
+            # build
+            _build_sim(platform, build_name, platform.sources, threads, coverage, verbose)
 
+        # run
         if run:
             _run_sim(build_name, as_root=sim_config.has_module("ethernet"))
 
         os.chdir("../../")
 
         if build:
-            return v_output.ns
\ No newline at end of file
+            return top_output.ns
\ No newline at end of file