From 58701cc48cd1778cec14196d86ab4d75d7c28624 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 25 Mar 2021 18:24:21 +0100 Subject: [PATCH] tools/litex_client: Use CSR base as base address on PCIe designs. --- litex/tools/litex_client.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/litex/tools/litex_client.py b/litex/tools/litex_client.py index b07fc4a5a..e8afd0ff6 100644 --- a/litex/tools/litex_client.py +++ b/litex/tools/litex_client.py @@ -90,6 +90,10 @@ def dump_identifier(port): wb = RemoteClient(port=port) wb.open() + # On PCIe designs, CSR is remapped to 0 to limit BAR0 size. + if hasattr(wb.bases, "pcie_phy"): + wb.base_address = -wb.mems.csr.base + fpga_identifier = "" for i in range(256): @@ -106,6 +110,10 @@ def dump_registers(port): wb = RemoteClient(port=port) wb.open() + # On PCIe designs, CSR is remapped to 0 to limit BAR0 size. + if hasattr(wb.bases, "pcie_phy"): + wb.base_address = -wb.mems.csr.base + for name, register in wb.regs.__dict__.items(): print("0x{:08x} : 0x{:08x} {}".format(register.addr, register.read(), name))