From 588b7a9519297fa71f4fc5362c7e9d348ea63f9f Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 6 May 2024 19:48:56 +0200 Subject: [PATCH] Update Vexii --- litex/soc/cores/cpu/vexiiriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 6cd7db20f..1c6cfea1a 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -130,7 +130,7 @@ class VexiiRiscv(CPU): print(args) if args.update_repo != "no": - NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "main", "af662e86" if args.update_repo=="recommended" else None) + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "b4e86579" if args.update_repo=="recommended" else None)