From 58f9a79cf398bd437d203695bdb0f86f91f81aa9 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 13 Jun 2022 22:49:14 +0800 Subject: [PATCH] cores/clock/intel_common: fix N factor not get passed to ALTPLL primitive The N factor is currently ignored when creating ALTPLL instance. As Quartus will internally decide N based on all dividers, just multiply N to all clock outputs' individual divider. Signed-off-by: Icenowy Zheng --- litex/soc/cores/clock/intel_common.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/clock/intel_common.py b/litex/soc/cores/clock/intel_common.py index 2017bb783..513c22cb2 100644 --- a/litex/soc/cores/clock/intel_common.py +++ b/litex/soc/cores/clock/intel_common.py @@ -79,7 +79,7 @@ class IntelClocking(Module, AutoCSR): diff = abs(clk_freq - f) if diff <= f*_m and diff < best_diff: config[f"clk{_n}_freq"] = clk_freq - config[f"clk{_n}_divide"] = c + config[f"clk{_n}_divide"] = c * n config[f"clk{_n}_phase"] = p clk_valid[_n] = True diff_ratios[_n] = diff / f