From 5a1925df2ef9e199bf3c64dc1ad9d9300aafbd85 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 20 Apr 2019 23:43:44 +0200 Subject: [PATCH] boards/targets: add keep attribute directly in crg This makes it systematic and avoid having to add it later. --- litex/boards/targets/arty.py | 9 +++++++-- litex/boards/targets/de0nano.py | 6 ++++++ litex/boards/targets/genesys2.py | 8 ++++++-- litex/boards/targets/kc705.py | 8 ++++++-- litex/boards/targets/kcu105.py | 8 +++++++- litex/boards/targets/minispartan6.py | 5 +++++ litex/boards/targets/nexys4ddr.py | 8 ++++++++ litex/boards/targets/nexys_video.py | 10 ++++++++-- litex/boards/targets/ulx3s.py | 3 +++ litex/boards/targets/versa_ecp5.py | 6 ++++++ 10 files changed, 62 insertions(+), 9 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 115df4017..c5a20ea2d 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -26,6 +26,13 @@ class _CRG(Module): self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() + # # # + + self.cd_sys.clk.attr.add("keep") + self.cd_sys4x.clk.attr.add("keep") + self.cd_sys4x_dqs.clk.attr.add("keep") + self.cd_clk200.clk.attr.add("keep") + self.submodules.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) @@ -95,10 +102,8 @@ class EthernetSoC(BaseSoC): self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) - self.crg.cd_sys.clk.attr.add("keep") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") - self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 80.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 80.0) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index 70b4a5c96..c51c1a116 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -60,6 +60,12 @@ class _CRG(Module): self.clock_domains.cd_sys_ps = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) + # # # + + self.cd_sys.clk.attr.add("keep") + self.cd_sys_ps.clk.attr.add("keep") + self.cd_por.clk.attr.add("keep") + clk50 = platform.request("clk50") sys_pll = _ALTPLL(20, "sys", 0, "NORMAL") diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index afe3992bb..150f830b5 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -25,6 +25,12 @@ class _CRG(Module): self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() + # # # + + self.cd_sys.clk.attr.add("keep") + self.cd_sys4x.clk.attr.add("keep") + self.cd_clk200.clk.attr.add("keep") + self.submodules.pll = pll = S7MMCM(speedgrade=-2) self.comb += pll.reset.eq(~platform.request("cpu_reset_n")) pll.register_clkin(platform.request("clk200"), 200e6) @@ -87,10 +93,8 @@ class EthernetSoC(BaseSoC): self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) - self.crg.cd_sys.clk.attr.add("keep") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") - self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index dc5d4e22c..0493db8c6 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -25,6 +25,12 @@ class _CRG(Module): self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() + # # # + + self.cd_sys.clk.attr.add("keep") + self.cd_sys4x.clk.attr.add("keep") + self.cd_clk200.clk.attr.add("keep") + self.submodules.pll = pll = S7MMCM(speedgrade=-2) self.comb += pll.reset.eq(platform.request("cpu_reset")) pll.register_clkin(platform.request("clk200"), 200e6) @@ -87,10 +93,8 @@ class EthernetSoC(BaseSoC): self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) - self.crg.cd_sys.clk.attr.add("keep") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") - self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 502af29ee..d676cff3d 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -26,6 +26,13 @@ class _CRG(Module): self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_ic = ClockDomain() + # # # + + self.cd_sys.clk.attr.add("keep") + self.cd_sys4x.clk.attr.add("keep") + self.cd_clk200.clk.attr.add("keep") + self.cd_ic.clk.attr.add("keep") + self.submodules.pll = pll = USMMCM(speedgrade=-2) self.comb += pll.reset.eq(platform.request("cpu_reset")) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) @@ -126,7 +133,6 @@ class EthernetSoC(BaseSoC): self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) - self.crg.cd_sys.clk.attr.add("keep") self.ethphy.cd_eth_rx.clk.attr.add("keep") self.ethphy.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6) diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 00cc506cf..2f3ed445d 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -21,6 +21,11 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain() + # # # + + self.cd_sys.clk.attr.add("keep") + self.cd_sys_ps.clk.attr.add("keep") + f0 = 32*1000000 clk32 = platform.request("clk32") clk32a = Signal() diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index e12098280..661aba182 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -25,6 +25,14 @@ class _CRG(Module): self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain() + # # # + + self.cd_sys.clk.attr.add("keep") + self.cd_sys2x.clk.attr.add("keep") + self.cd_sys2x_dqs.clk.attr.add("keep") + self.cd_clk200.clk.attr.add("keep") + self.cd_clk100.clk.attr.add("keep") + self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 902d2ec50..db94b9f63 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -27,6 +27,14 @@ class _CRG(Module): self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain() + # # # + + self.cd_sys.clk.attr.add("keep") + self.cd_sys4x.clk.attr.add("keep") + self.cd_sys4x_dqs.clk.attr.add("keep") + self.cd_clk200.clk.attr.add("keep") + self.cd_clk100.clk.attr.add("keep") + self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) @@ -91,10 +99,8 @@ class EthernetSoC(BaseSoC): self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) - self.crg.cd_sys.clk.attr.add("keep") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") - self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index ed7e7350c..ec54c406e 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -23,6 +23,9 @@ class _CRG(Module): # # # + self.cd_sys.clk.attr.add("keep") + self.cd_sys_ps.clk.attr.add("keep") + # clk / rst clk25 = platform.request("clk25") rst = platform.request("rst") diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index f82e42e80..6331d4a12 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -30,6 +30,12 @@ class _CRG(Module): # # # + self.cd_init.clk.attr.add("keep") + self.cd_por.clk.attr.add("keep") + self.cd_sys.clk.attr.add("keep") + self.cd_sys2x.clk.attr.add("keep") + self.cd_sys2x_i.clk.attr.add("keep") + self.stop = Signal() # clk / rst