From 5a2c92ba804caa8be27947ea5755df08c4d442da Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 18 Dec 2017 20:36:59 -0500
Subject: [PATCH] Add TinyFPGA platform based on Migen.

---
 litex/boards/platforms/tinyfpga_b.py | 40 ++++++++++++++++++++++++++++
 litex/build/lattice/programmer.py    | 15 +++++++++++
 2 files changed, 55 insertions(+)
 create mode 100644 litex/boards/platforms/tinyfpga_b.py

diff --git a/litex/boards/platforms/tinyfpga_b.py b/litex/boards/platforms/tinyfpga_b.py
new file mode 100644
index 000000000..d99be7422
--- /dev/null
+++ b/litex/boards/platforms/tinyfpga_b.py
@@ -0,0 +1,40 @@
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+from litex.build.lattice.programmer import TinyFpgaBProgrammer
+
+_io = [
+    ("usb", 0,
+        Subsignal("d_p", Pins("A3")),
+        Subsignal("d_n", Pins("A4")),
+        IOStandard("LVCMOS33")
+    ),
+
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")),
+        Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")),
+        Subsignal("mosi", Pins("G6"), IOStandard("LVCMOS33")),
+        Subsignal("miso", Pins("H7"), IOStandard("LVCMOS33"))
+    ),
+
+    ("clk16", 0, Pins("B4"), IOStandard("LVCMOS33"))
+]
+
+_connectors = [
+    # B2-J1, Pins 4-13
+    # D9-C9, Pins 18-19, Pins 21-24
+    # E8, Pin 20 (Input only)
+    ("GPIO", "B2 A2 A1 B1 C1 D1 E1 G1 H1 J1 D9 C9 A9 A8 A7 A6"),
+    ("GBIN", "E8")
+]
+
+
+class Platform(LatticePlatform):
+    default_clk_name = "clk16"
+    default_clk_period = 62.5
+
+    def __init__(self):
+        LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors,
+                                 toolchain="icestorm")
+
+    def create_programmer(self):
+        return TinyFpgaBProgrammer()
diff --git a/litex/build/lattice/programmer.py b/litex/build/lattice/programmer.py
index 94282d42c..e9e5791b4 100644
--- a/litex/build/lattice/programmer.py
+++ b/litex/build/lattice/programmer.py
@@ -41,3 +41,18 @@ class IceBurnProgrammer(GenericProgrammer):
 
     def load_bitstream(self, bitstream_file):
         subprocess.call([self.iceburn, "-evw", bitstream_file])
+
+
+class TinyFpgaBProgrammer(GenericProgrammer):
+    needs_bitreverse = False
+
+    # The default flash address you probably want is 0x30000; the image at
+    # address 0 is for the bootloader.
+    def flash(self, address, bitstream_file):
+        subprocess.call(["tinyfpgab", "-a", str(address), "-p",
+                        bitstream_file])
+
+    # Force user image to boot if a user reset tinyfpga, the bootloader
+    # is active, and the user image need not be reprogrammed.
+    def boot(self):
+        subprocess.call(["tinyfpgab", "-b"])