From 5a402264d0416f4e1af3c122807a505383e7d4ba Mon Sep 17 00:00:00 2001
From: bunnie <bunnie@kosagi.com>
Date: Tue, 24 Mar 2020 14:11:23 +0800
Subject: [PATCH] Fix off-by-one error on almost full condition for prefetch

This causes a DRC error on the Xilinx tools when the prefetch
lines setting is 1. Don't know why this wasn't caught earlier,
but it just popped up in CI.
---
 litex/soc/cores/spi_opi.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/spi_opi.py b/litex/soc/cores/spi_opi.py
index 45f477677..8e87518f8 100644
--- a/litex/soc/cores/spi_opi.py
+++ b/litex/soc/cores/spi_opi.py
@@ -494,7 +494,7 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc):
                 p_DATA_WIDTH              = 32,
                 p_FIRST_WORD_FALL_THROUGH = "TRUE",
                 p_ALMOST_EMPTY_OFFSET     = 6,
-                p_ALMOST_FULL_OFFSET      = (512- (8*prefetch_lines)),
+                p_ALMOST_FULL_OFFSET      = (511 - (8*prefetch_lines)),
 
                 o_ALMOSTEMPTY = rx_almostempty,
                 o_ALMOSTFULL  = rx_almostfull,