From 5af8e5c9345053763f6d89764790a7fc8793b8bf Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 8 Mar 2021 13:46:56 +0100
Subject: [PATCH] soc/add_etherbone: Fix UDPIPCore clock domain (should still
 run at eth_clk even if Etherbone is running in sys_clk) since data-width
 convertion is done on UDP.

---
 litex/soc/integration/soc.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index e9a61aaaa..9660859e8 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1408,7 +1408,8 @@ class LiteXSoC(SoC):
             clk_freq    = self.clk_freq)
         ethcore = ClockDomainsRenamer({
             "eth_tx": phy_cd + "_tx",
-            "eth_rx": phy_cd + "_rx"})(ethcore)
+            "eth_rx": phy_cd + "_rx",
+            "sys":    phy_cd + "_rx"})(ethcore)
         self.submodules.ethcore = ethcore
 
         # Clock domain renaming