diff --git a/examples/de1/client/test_MigLa.py b/examples/de1/client/test_MigLa.py
new file mode 100644
index 000000000..5ea76d602
--- /dev/null
+++ b/examples/de1/client/test_MigLa.py
@@ -0,0 +1,69 @@
+from migen.fhdl.structure import *
+from migen.fhdl import verilog, autofragment
+from migen.bus import csr
+from migen.bus.transactions import *
+from migen.bank import description, csrgen
+from migen.bank.description import *
+
+import sys
+sys.path.append("../../../")
+
+from migScope import trigger, recorder, migIo
+from migScope.tools.truthtable import *
+import spi2Csr
+from spi2Csr.tools.uart2Spi import *
+
+#==============================================================================
+#	P A R A M E T E R S
+#==============================================================================
+# Bus Width
+trig_width = 16
+dat_width = 16
+
+# Record Size
+record_size = 1024
+
+# Csr Addr
+MIGIO0_ADDR   = 0x0000
+TRIGGER_ADDR  = 0x0200
+RECORDER_ADDR = 0x0400
+
+csr = Uart2Spi(1,115200)
+
+# MigScope Configuration
+# migIo
+migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr)
+
+# Trigger
+term0 = trigger.Term(trig_width)
+term1 = trigger.Term(trig_width)
+term2 = trigger.Term(trig_width)
+term3 = trigger.Term(trig_width)
+trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0, term1, term2, term3], csr)
+
+# Recorder
+recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size, csr)
+
+#==============================================================================
+#                  T E S T  M I G L A 
+#==============================================================================
+
+term0.write(0x5A)
+term1.write(0x5A)
+term2.write(0x5A)
+term3.write(0x5A)
+sum_tt = gen_truth_table("term0 & term1 & term2 & term3")
+print(sum_tt)
+trigger0.sum.write(sum_tt)
+
+migIo0.write(0x5A)
+
+recorder0.reset()
+recorder0.size(256)
+recorder0.offset(0)
+recorder0.arm()
+
+while(not recorder0.is_done()):
+	print(".")
+	time.sleep(1)
+
diff --git a/examples/de1/top.py b/examples/de1/top.py
index f690bb9c7..b13b0a322 100644
--- a/examples/de1/top.py
+++ b/examples/de1/top.py
@@ -89,7 +89,7 @@ def get():
 	recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size)
 	
 	# Spi2Csr
-	spi2csr0 = spi2Csr.Spi2Csr(14,8)
+	spi2csr0 = spi2Csr.Spi2Csr(16,8)
 	
 	# Csr Interconnect
 	csrcon0 = csr.Interconnect(spi2csr0.csr, 
@@ -109,7 +109,7 @@ def get():
 	
 	# Led
 	led0 = Signal(BV(8))
-	comb += [led0.eq(migIo0.o[:8])]
+	#comb += [led0.eq(migIo0.o[:8])]
 	
 	#Switch
 	sw0 = Signal(BV(8))
@@ -124,13 +124,13 @@ def get():
 		trigger0.in_trig.eq(sig_gen),
 		trigger0.in_dat.eq(sig_gen)
 	]
-	#comb += [led0[7].eq(trigger0.sum.i)]
-	#comb += [led0[6].eq(trigger0.sum.o)]
+	comb += [led0[7].eq(trigger0.sum.i)]
+	comb += [led0[6].eq(trigger0.sum.o)]
 	
-	#comb += [led0[3].eq(term3.o)]
-	#comb += [led0[2].eq(term2.o)]
-	#comb += [led0[1].eq(term1.o)]
-	#comb += [led0[0].eq(term0.o)]
+	comb += [led0[3].eq(term3.o)]
+	comb += [led0[2].eq(term2.o)]
+	comb += [led0[1].eq(term1.o)]
+	comb += [led0[0].eq(term0.o)]
 	
 	# Trigger --> Recorder	
 	comb += [
diff --git a/migScope/migIo.py b/migScope/migIo.py
index 373ed44e8..72024d5bc 100644
--- a/migScope/migIo.py
+++ b/migScope/migIo.py
@@ -25,8 +25,7 @@ class MigIo:
 			self.interface.write_n(self.address, data, self.width)
 			
 	def read(self):
-		r = 0
-			r = self.interface.read_n(self.address + self.words, self.width)
+		r = self.interface.read_n(self.address + self.words, self.width)
 		return r
 				
 	def get_fragment(self):
diff --git a/spi2Csr/tools/arduino/uart2Spi.pde b/spi2Csr/tools/arduino/uart2Spi.pde
index 38cec1c40..df049bfdd 100644
--- a/spi2Csr/tools/arduino/uart2Spi.pde
+++ b/spi2Csr/tools/arduino/uart2Spi.pde
@@ -44,5 +44,8 @@ void loop()
      data = SF.rd(addrMsb<<8|addrLsb);
      Serial.print(data);
    }
+   else {
+     Serial.flush();
+   }
  }
 }
\ No newline at end of file