diff --git a/misoclib/com/liteeth/core/__init__.py b/misoclib/com/liteeth/core/__init__.py
index 10bd2f907..834513165 100644
--- a/misoclib/com/liteeth/core/__init__.py
+++ b/misoclib/com/liteeth/core/__init__.py
@@ -9,7 +9,7 @@ from misoclib.com.liteeth.core.icmp import LiteEthICMP
 
 class LiteEthIPCore(Module, AutoCSR):
     def __init__(self, phy, mac_address, ip_address, clk_freq):
-        self.submodules.mac = LiteEthMAC(phy, 8, interface="crossbar", with_hw_preamble_crc=True)
+        self.submodules.mac = LiteEthMAC(phy, 8, interface="crossbar", with_preamble_crc=True)
         self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address, clk_freq)
         self.submodules.ip = LiteEthIP(self.mac, mac_address, ip_address, self.arp.table)
         self.submodules.icmp = LiteEthICMP(self.ip, ip_address)
diff --git a/misoclib/com/liteeth/mac/__init__.py b/misoclib/com/liteeth/mac/__init__.py
index 7611f192e..f951c38b3 100644
--- a/misoclib/com/liteeth/mac/__init__.py
+++ b/misoclib/com/liteeth/mac/__init__.py
@@ -7,8 +7,8 @@ from misoclib.com.liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterfa
 
 class LiteEthMAC(Module, AutoCSR):
     def __init__(self, phy, dw, interface="crossbar", endianness="big",
-            with_hw_preamble_crc=True):
-        self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_hw_preamble_crc)
+            with_preamble_crc=True):
+        self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc)
         self.csrs = []
         if interface == "crossbar":
             self.submodules.crossbar = LiteEthMACCrossbar()
diff --git a/misoclib/com/liteeth/test/arp_tb.py b/misoclib/com/liteeth/test/arp_tb.py
index f7b768550..f4b1fee48 100644
--- a/misoclib/com/liteeth/test/arp_tb.py
+++ b/misoclib/com/liteeth/test/arp_tb.py
@@ -20,7 +20,7 @@ class TB(Module):
         self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
         self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
 
-        self.submodules.mac = LiteEthMAC(self.phy_model, dw=8, with_hw_preamble_crc=True)
+        self.submodules.mac = LiteEthMAC(self.phy_model, dw=8, with_preamble_crc=True)
         self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address, 100000)
 
         # use sys_clk for each clock_domain
diff --git a/misoclib/com/liteeth/test/mac_core_tb.py b/misoclib/com/liteeth/test/mac_core_tb.py
index d836fe669..c852417d3 100644
--- a/misoclib/com/liteeth/test/mac_core_tb.py
+++ b/misoclib/com/liteeth/test/mac_core_tb.py
@@ -14,7 +14,7 @@ class TB(Module):
     def __init__(self):
         self.submodules.phy_model = phy.PHY(8, debug=False)
         self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=True)
-        self.submodules.core = LiteEthMACCore(phy=self.phy_model, dw=8, with_hw_preamble_crc=True)
+        self.submodules.core = LiteEthMACCore(phy=self.phy_model, dw=8, with_preamble_crc=True)
 
         self.submodules.streamer = PacketStreamer(eth_phy_description(8), last_be=1)
         self.submodules.streamer_randomizer = AckRandomizer(eth_phy_description(8), level=50)
diff --git a/misoclib/com/liteeth/test/mac_wishbone_tb.py b/misoclib/com/liteeth/test/mac_wishbone_tb.py
index 424e3ba4c..cfc1efdc7 100644
--- a/misoclib/com/liteeth/test/mac_wishbone_tb.py
+++ b/misoclib/com/liteeth/test/mac_wishbone_tb.py
@@ -85,7 +85,7 @@ class TB(Module):
     def __init__(self):
         self.submodules.phy_model = phy.PHY(8, debug=False)
         self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=True)
-        self.submodules.ethmac = LiteEthMAC(phy=self.phy_model, dw=32, interface="wishbone", with_hw_preamble_crc=True)
+        self.submodules.ethmac = LiteEthMAC(phy=self.phy_model, dw=32, interface="wishbone", with_preamble_crc=True)
 
         # use sys_clk for each clock_domain
         self.clock_domains.cd_eth_rx = ClockDomain()
diff --git a/targets/simple.py b/targets/simple.py
index 095ab910a..62ea87ce3 100644
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -41,7 +41,7 @@ class MiniSoC(BaseSoC):
                                             platform.request("eth"))
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
                                             interface="wishbone",
-                                            with_hw_preamble_crc=False)
+                                            with_preamble_crc=False)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)