From 5bbcda4d5ca53f7a36e4499cb4d3e970f7d2d328 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 4 Jan 2024 13:09:31 +0100 Subject: [PATCH] interconnect/ahb/AHB2Wishbone: Fix size check that is too restrictive, can be <= log2_int(ahb.data_width//8). --- litex/soc/interconnect/ahb.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/interconnect/ahb.py b/litex/soc/interconnect/ahb.py index a39d3d2e2..e7c73f238 100644 --- a/litex/soc/interconnect/ahb.py +++ b/litex/soc/interconnect/ahb.py @@ -70,7 +70,7 @@ class AHB2Wishbone(LiteXModule): fsm.act("IDLE", ahb.readyout.eq(1), If(ahb.sel & - (ahb.size == wishbone_adr_shift) & + (ahb.size <= log2_int(ahb.data_width//8)) & (ahb.trans == TransferType.NONSEQUENTIAL), NextValue(wishbone.adr, ahb.addr[wishbone_adr_shift:]), NextValue(wishbone.dat_w, ahb.wdata),