From 4a3454107ac13bdd07348fab06fb6ade3908917f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 12 Jan 2018 13:33:13 +1100 Subject: [PATCH] fix DDR3 on nexys_video --- litex/boards/targets/nexys_video.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 77b54688b..daa9c9803 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -97,8 +97,8 @@ class BaseSoC(SoCSDRAM): # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) - self.add_constant("A7DDRPHY_BITSLIP", 3) - self.add_constant("A7DDRPHY_DELAY", 14) + self.add_constant("READ_LEVELING_BITSLIP", 3) + self.add_constant("READ_LEVELING_DELAY", 14) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings,