From 5cc564fb8f302f7a5a37e3b6710c6baedbf9f097 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 29 May 2020 19:22:35 +0200 Subject: [PATCH] targets: simplify Ethernet/Etherbone integration on targets with both. --- litex/boards/targets/arty.py | 17 ++++++----------- litex/boards/targets/genesys2.py | 17 ++++++----------- 2 files changed, 12 insertions(+), 22 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 98d2e3be7..fe6c8f522 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -79,21 +79,16 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) - # Ethernet --------------------------------------------------------------------------------- - if with_ethernet: + # Ethernet / Etherbone --------------------------------------------------------------------- + if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) self.add_csr("ethphy") - self.add_ethernet(phy=self.ethphy) - - # Etherbone -------------------------------------------------------------------------------- - if with_etherbone: - self.submodules.ethphy = LiteEthPHYMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - self.add_etherbone(phy=self.ethphy) + if with_ethernet: + self.add_ethernet(phy=self.ethphy) + if with_etherbone: + self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 4e5e823be..5f96101cc 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -70,21 +70,16 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) - # Ethernet --------------------------------------------------------------------------------- - if with_ethernet: + # Ethernet / Etherbone --------------------------------------------------------------------- + if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) self.add_csr("ethphy") - self.add_ethernet(phy=self.ethphy) - - # Etherbone -------------------------------------------------------------------------------- - if with_etherbone: - self.submodules.ethphy = LiteEthPHYRGMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - self.add_etherbone(phy=self.ethphy) + if with_ethernet: + self.add_ethernet(phy=self.ethphy) + if with_etherbone: + self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(