From 5d1fa7b6cadcc384e289ac125f838eb9e8cd96df Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Sun, 25 Feb 2024 11:15:38 +1100 Subject: [PATCH] cores/spi_mmap: fix data if bus width > length Details: * 32bit bus write to 8 and 16bit MSB first slot resulted in shifted data on mosi. * 32bit read from 8 and 16bit LSB first slot resulted with shifted data in fifo. Fixes 2 tests - all current tests now pass. --- litex/soc/cores/spi/spi_mmap.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/spi/spi_mmap.py b/litex/soc/cores/spi/spi_mmap.py index 17b2ca8c0..58ea9e1fd 100644 --- a/litex/soc/cores/spi/spi_mmap.py +++ b/litex/soc/cores/spi/spi_mmap.py @@ -591,7 +591,7 @@ class SPIEngine(LiteXModule): # MSB First. If(spi_bitorder == SPI_SLOT_BITORDER_MSB_FIRST, # TX copy/bitshift. - Case(spi_length, { + Case(spi.length, { 8 : spi.mosi[24:32].eq(sink.data[0: 8]), 16 : spi.mosi[16:32].eq(sink.data[0:16]), 32 : spi.mosi[ 0:32].eq(sink.data[0:32]), @@ -604,7 +604,7 @@ class SPIEngine(LiteXModule): # TX copy. spi.mosi.eq(sink.data[::-1]), # RX copy/bitshift. - Case(spi_length, { + Case(spi.length, { 8 : source.data[0: 8].eq(spi.miso[::-1][24:32]), 16 : source.data[0:16].eq(spi.miso[::-1][16:32]), 32 : source.data[0:32].eq(spi.miso[::-1][ 0:32]),