diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 1116fa2f4..62e2ad775 100755
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -68,7 +68,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, toolchain, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs):
+    def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs):
         platform = arty.Platform(toolchain=toolchain)
 
         # SoCCore ----------------------------------------------------------------------------------
diff --git a/test/test_targets.py b/test/test_targets.py
index ddf2788bd..ded185aa4 100644
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -74,9 +74,9 @@ class TestTargets(unittest.TestCase):
         self.assertEqual(errors, 0)
 
     def test_arty_symbiflow(self):
-        from litex.boards.targets.arty_symbiflow import BaseSoC
+        from litex.boards.targets.arty import BaseSoC
         errors = build_test([
-            BaseSoC(**test_kwargs)
+            BaseSoC(toolchain="symbiflow", **test_kwargs)
         ])
         self.assertEqual(errors, 0)