diff --git a/litex/build/efinix/ifacewriter.py b/litex/build/efinix/ifacewriter.py
index 5755e0d3c..19abebc8b 100644
--- a/litex/build/efinix/ifacewriter.py
+++ b/litex/build/efinix/ifacewriter.py
@@ -328,8 +328,8 @@ design.create('{2}', '{3}', './../gateware', overwrite=True)
             cmd += 'design.set_property("{}", "CORE_CLK_PIN", "{}", block_type="PLL")\n\n'.format(name, block['input_signal'])
 
         cmd += 'design.set_property("{}","LOCKED_PIN","{}", block_type="PLL")\n'.format(name, block['locked'])
-        if block['reset'] != '':
-            cmd += 'design.set_property("{}","RSTN_PIN","{}", block_type="PLL")\n\n'.format(name, block['reset'])
+        if block['rstn'] != '':
+            cmd += 'design.set_property("{}","RSTN_PIN","{}", block_type="PLL")\n\n'.format(name, block['rstn'])
 
          # Output clock 0 is enabled by default
         for i, clock in enumerate(block['clk_out']):
diff --git a/litex/soc/cores/clock/efinix_trion.py b/litex/soc/cores/clock/efinix_trion.py
index d226f9536..d7bddc48c 100644
--- a/litex/soc/cores/clock/efinix_trion.py
+++ b/litex/soc/cores/clock/efinix_trion.py
@@ -17,7 +17,7 @@ class Open(Signal): pass
 
 class TRIONPLL(Module):
     nclkouts_max = 4
-    def __init__(self, platform, with_reset=False):
+    def __init__(self, platform):
         self.logger = logging.getLogger("TRIONPLL")
         self.logger.info("Creating TRIONPLL.".format())
         self.platform   = platform
@@ -26,26 +26,19 @@ class TRIONPLL(Module):
         self.reset      = Signal()
         self.locked     = Signal()
 
+        # Create PLL block.
         block = {}
-
-        block["type"] = "PLL"
-        block["name"] = self.pll_name
+        block["type"]    = "PLL"
+        block["name"]    = self.pll_name
         block["clk_out"] = []
-
-        pll_locked_name = self.pll_name + "_locked"
-        block["locked"] = pll_locked_name
-        io = self.platform.add_iface_io(pll_locked_name)
-        self.comb += self.locked.eq(io)
-
-        block["reset"] = ""
-        if with_reset:
-            pll_reset_name = self.pll_name + "_reset"
-            block["reset"] = pll_reset_name
-            io = self.platform.add_iface_io(pll_reset_name)
-            self.comb += io.eq(self.reset)
-
+        block["locked"]  = self.pll_name + "_locked"
+        block["rstn"]    = self.pll_name + "_rstn"
         self.platform.toolchain.ifacewriter.blocks.append(block)
 
+        # Connect PLL's rstn/locked.
+        self.comb += self.platform.add_iface_io(self.pll_name + "_rstn").eq(~self.reset)
+        self.comb += self.locked.eq(self.platform.add_iface_io(self.pll_name + "_locked"))
+
     def register_clkin(self, clkin, freq, name= ""):
         block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)