From 5e2e9338d21ce52e2fb895a9c59fd0c51aff34d2 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 27 Feb 2015 17:22:44 +0100
Subject: [PATCH] bios: we can now use -Ot with_rom True on targets to force
 bios implementation in integrated rom (can speed up debug we don't want to
 reflash SPI or NOR flash)

---
 targets/kc705.py       | 19 ++++++++++---------
 targets/mlabs_video.py | 10 ++++++----
 targets/pipistrello.py |  9 +++++----
 targets/ppro.py        |  9 +++++----
 4 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/targets/kc705.py b/targets/kc705.py
index ddbe406f7..54b287717 100644
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -98,15 +98,16 @@ class BaseSoC(SDRAMSoC):
 		self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
 		self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
 
-		# BIOS is in SPI flash
-		spiflash_pads = platform.request("spiflash")
-		spiflash_pads.clk = Signal()
-		self.specials += Instance("STARTUPE2",
-			i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
-			i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
-		self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
-		self.flash_boot_address = 0xb00000
-		self.register_rom(self.spiflash.bus)
+		# If not in ROM, BIOS is in SPI flash
+		if not self.with_rom:
+			spiflash_pads = platform.request("spiflash")
+			spiflash_pads.clk = Signal()
+			self.specials += Instance("STARTUPE2",
+				i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
+				i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
+			self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
+			self.flash_boot_address = 0xb00000
+			self.register_rom(self.spiflash.bus)
 
 class MiniSoC(BaseSoC):
 	csr_map = {
diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index a6dab0a6f..664caafd2 100644
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -54,10 +54,12 @@ class BaseSoC(SDRAMSoC):
 			rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
 		self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
 
-		self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
-			self.ns(110), self.ns(50))
-		self.flash_boot_address = 0x001a0000
-		self.register_rom(self.norflash.bus)
+		# If not in ROM, BIOS is in // NOR flash
+		if not self.with_rom:
+			self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
+				self.ns(110), self.ns(50))
+			self.flash_boot_address = 0x001a0000
+			self.register_rom(self.norflash.bus)
 
 		self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
 		self.comb += [
diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 4d7673ec2..a259083a4 100644
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -97,9 +97,10 @@ class BaseSoC(SDRAMSoC):
 		self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
 		self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing)
 
-		# BIOS is in SPI flash
-		self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
-		self.flash_boot_address = 0x70000
-		self.register_rom(self.spiflash.bus)
+		# If not in ROM, BIOS is in SPI flash
+		if not self.with_rom:
+			self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
+			self.flash_boot_address = 0x70000
+			self.register_rom(self.spiflash.bus)
 
 default_subtarget = BaseSoC
diff --git a/targets/ppro.py b/targets/ppro.py
index a6f59d32c..d9b1dad89 100644
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -91,9 +91,10 @@ class BaseSoC(SDRAMSoC):
 		self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
 		self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing)
 
-		# BIOS is in SPI flash
-		self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
-		self.flash_boot_address = 0x70000
-		self.register_rom(self.spiflash.bus)
+		# If not in ROM, BIOS is in SPI flash
+		if not self.with_rom:
+			self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
+			self.flash_boot_address = 0x70000
+			self.register_rom(self.spiflash.bus)
 
 default_subtarget = BaseSoC