From 5e3e78f7604ede526a6946b6ff4e601018f4fb45 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 12 Oct 2021 15:38:39 +0200
Subject: [PATCH] soc/add_pcie: Automatically set Endpoint's endianness to
 PHY's endianness.

---
 litex/soc/integration/soc.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 0c80a88d4..524f229c7 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1695,7 +1695,7 @@ class LiteXSoC(SoC):
 
         # Endpoint.
         self.check_if_exists(f"{name}_endpoint")
-        endpoint = LitePCIeEndpoint(phy, max_pending_requests=max_pending_requests)
+        endpoint = LitePCIeEndpoint(phy, max_pending_requests=max_pending_requests, endianness=phy.endianness)
         setattr(self.submodules, f"{name}_endpoint", endpoint)
 
         # MMAP.